Creating a new 020 accel board for A600 (eventually to A500 too)

[rkauer]

Originally Posted by FrenchShark

Hello,

I have just looked at the A500 motherboard on the big book of amiga hardware. Since the 68000 is located close to the edge of the MB, it is pretty easy to make an adapter for the stratix board (the dev board has 80 5V tolerant IO pins).
This way, I can spy the 68000 running (the FPGA acts as a logic analyzer), then, I can replace it with the FPGA on the dev board.

So I am looking for an A500 motherboard (I only owned A2000s and A1200s).
I live in the US (Huntsville, AL).

Regards,

Frederic

Hello Frederic.

The A2000 is basically an A500 with a Zorro bus board. The CPU slot have all pins you need to build a logic analyser.

But if you don't want to risk your A2000...

-------

Minor update to the design: investigating those CPLD "Cool Runner" (SCR3xxx family), I didn't found any SDRAM controller. Only for "bulked" FPGAs... Sad! Damn! I'll hate to make it from scratch!

BTW: all CPLD SDRAM controllers I've found are intended for PPC CPUs!

NO! I don't want to build a PPC for the A500/600!

[FrenchShark]

Originally Posted by rkauer

Hello Frederic.

The A2000 is basically an A500 with a Zorro bus board. The CPU slot have all pins you need to build a logic analyser.

But if you don't want to risk your A2000...

-------

Minor update to the design: investigating those CPLD "Cool Runner" (SCR3xxx family), I didn't found any SDRAM controller. Only for "bulked" FPGAs... Sad! Damn! I'll hate to make it from scratch!

BTW: all CPLD SDRAM controllers I've found are intended for PPC CPUs!

NO! I don't want to build a PPC for the A500/600!

Well,
I do not have my A2000 here, it stayed in France...
Moreover, on the A2000, the CPU is in the middle of the motherboard (and even under the floppies/PSU support IIRC).
The A500 has the advantage of having the CPU close to the edge of the motherboard. The stratix dev board has the expansion connectors on one side too.
So a pretty cheap PCB with short traces can be made to connect the stratix board to the A500.
I could use some ribbon cables but this is usually not good for signal integrity.
That's why I am looking for an A500.

Regards,

Frederic

[FrenchShark]

Originally Posted by rkauer

Good point, but sharing the data bus will bring more problems in the design. Better have another CPLD with enough pins (QFPGA, of course) or use a real 68k chip (the cheaper, the better).

OR use the CPLD only for the actual CPU emulation. Lots of extra space inside. Shame SATA use a lot of the space inside the chip for it alone...

BTW: Audio??? I think Paula is good enough for an A500/600. But if you mean MP3 decoding.... Hmm........... I like the sound of this idea!

With a 020/030, the databus is shared anyway.
I took a look at the hi-res pictures of A500 accel boards on the Big Book of Amiga.
You can learn a lot of interresting things: for example the use of 74ACT646 buffer. For a 3.3V design this will be a 74LVC646 (5V tolerant !). The advantage of this chip over the mosfet switch I have mentioned before is that it has integrated latches. Digikey price : $1.26

For the audio I was thinking about putting Super Paula audio with a DSP for mp3 decoding. This must fit into a EP3C10 without problem.

Regards,

Frederic

[FrenchShark]

Hello,

I have quickly checked the A500 schematics.
I have found out that the following signals are not used (providing you have nothing connected on the side expansion port) :
- FC0 - FC2
- BG#, BR#, BGACK#, BERR# (funny, CBM engineers called it BEER)
- HLT# maybe ?
- If you re-do in the FPGA the address decoding for the 8520s, you do not need VPA# from Gary.
In conclusion, only 51 IOs are needed for the 68000 bus.

Now, it's time for bed.

Frederic

[yaqube]

Over ten years ago I made an adapter board to accommodate an A600 accelerator in my A500. It had also two A600-style IDE ports. Unfortunately the schematics are gone and I can't find any GAL sources. But I remember the BR# was used by the accelerator board to three-state (disable) the on-board CPU.

Moreover the A600 design doesn't use VPA#/VMA# to communicate with CIAs. Those cycles are terminated by DTACK# (generated by Gayle) synced appropriately with E clock. But to be used in A500 the accelerator must generate VMA# in response to VPA# and it is what my adapter board did.

Another interesting feature is that the Amiga doesn't use autovectored interrupts. The interrupt acknowlegde cycle is terminated by DTACK# and interrupt vector is read from ROM (have a look at the last 7 words in any kickstart rom).

I hope it will help a little. At that time I wanted to build my own 030 accelerator for my A500 because I couldn't buy any but in the end I bought an Apollo 630 and made the above-mentioned adapter board .

[Zetr0]

@yaqube

awesome, i would love to see some hardware pr0n for that

I am interested in the VPA/VMA signals you mention, as the 68000NF8 and 680000 in the A500 / A600, are identical in operation.

if there is need for more logic / glue for the a500 version then any sources you have is good and much appreciated

I was lucky enough to work with Narmi, on an A600 Chip Package Changer ( converted it to 64Pin DIP format) to allow for a500 ram upgrades etc, and from this developed the cpu handshaking from the on-board to the new one.

[yaqube]

hardware pr0n for Zetr0

[Zetr0]

!!!AWESOME!!!

Thank you muchly! it looks absolutely awesome!

[rkauer]

Originally Posted by FrenchShark

Hello,

I have quickly checked the A500 schematics.
I have found out that the following signals are not used (providing you have nothing connected on the side expansion port) :
- FC0 - FC2
- BG#, BR#, BGACK#, BERR# (funny, CBM engineers called it BEER)
- HLT# maybe ?
- If you re-do in the FPGA the address decoding for the 8520s, you do not need VPA# from Gary.
In conclusion, only 51 IOs are needed for the 68000 bus.

Now, it's time for bed.

Frederic

Fred, the BG#, BR#, BGACK# signals are need for any accelerator to work! All of 'em, unfortunately.

Namely: BR is "bus request" (an external device is asking to control the bus itself), BG is "bus granted", BGACK is "bus grant acknowledgement" (the external device - in this case, the accelerator - responds to CPU).

Beer is fundamental, at least for drinking while the design advances! No joking: bus error (BERR) is needed, too. Without it, no RAM controller (or any controller, for that matter) can inform the CPU for errors in reads and writes.

[FrenchShark]

Originally Posted by rkauer

Fred, the BG#, BR#, BGACK# signals are need for any accelerator to work! All of 'em, unfortunately.

Namely: BR is "bus request" (an external device is asking to control the bus itself), BG is "bus granted", BGACK is "bus grant acknowledgement" (the external device - in this case, the accelerator - responds to CPU).

Beer is fundamental, at least for drinking while the design advances! No joking: bus error (BERR) is needed, too. Without it, no RAM controller (or any controller, for that matter) can inform the CPU for errors in reads and writes.

Hello,

I guess that to take over the 68000, you always maintain BR# low.
So it is not really a signal from the FPGA point of view.
Moreover, this is only valid for the A600 (since the 68000 is soldered).
On the A500 & A2000, the 68000 won't be put back on the accelerator board since the FPGA IS a 68000. You just need to reprogram the FPGA PLL to slow down the VHDL CPU to 7MHz for compatibility mode.

BERR# is to used to generate a guru when the CPU accesses a non existing memory location. This is rarelly used on Amiga system. I remember the A500+ having pull-up resistors on the data bus that generate RTS instruction on empty memory ranges.

Regards,

Frederic

[Zetr0]

Hello there my friends,

Okay here is a collection of similar and useful projects that coincide with this one. I do hope there of use.

First the SCRAM500 project: by Will McGovern & Norman Jackson

The SCRAM500 Is an 8Meg RAM and SCSI controller for the Amiga 500 (SCsi RAM for the 500 = SCRAM 500) connecting to the zorro expansion bus. The SCRAM 500 is easy to build, cheap and should be useful to a lot of people. There is a lot of information in this file, so have fun!

SCRAM500

LUCAS

FRANCES &FRANCES 2.0

PC Reworked Schematics (CPU/PALS/GLUE and Logic

okay thats to begin with, I will add more to this archive as time and the project continue.

Currently I am hunting/sourcing for the "SCRAMJet" project also by Will McGovern & Norman Jackson. alas my attemps at locating it are falling short

[rkauer]

Some good news: I found two PGA "full" 020!

They are mine! Mine!

So I will start the schematics from where it supposed to be: from a real 68k CPU and the RAM controller (in a humble CPLD). I catch a SDRAM controller intended for PPC cards. So everybody expect a little improvements on this area!

[rkauer]

OK: just to update the thread, I wish share what I have until now.

I got a source of PGA 020 (OK, not the speed devil I want, but...).

So I start thinking with myself (no, I'm not schizo, I'm taking my pills !), why not dismember this project in two?


One EC020 PLCC or PGA, allowing up to 8Mb of FAST SRAM (more static memory can be too way expensive!), other with full 020 or 030, one or two CPLD to control SDRAM DIMM memory (adding a lot of complexity to the design). I will use the Zetr0's Tornado board as a start point (my skills in Eagle/FreePCB sucks).

So everybody, expect some schematics pron soon!

[FrenchShark]

Originally Posted by rkauer

OK: just to update the thread, I wish share what I have until now.

I got a source of PGA 020 (OK, not the speed devil I want, but...).

So I start thinking with myself (no, I'm not schizo, I'm taking my pills !), why not dismember this project in two?


One EC020 PLCC or PGA, allowing up to 8Mb of FAST SRAM (more static memory can be too way expensive!), other with full 020 or 030, one or two CPLD to control SDRAM DIMM memory (adding a lot of complexity to the design). I will use the Zetr0's Tornado board as a start point (my skills in Eagle/FreePCB sucks).

So everybody, expect some schematics pron soon!

Hello rkauer,

do you plan to use the CY7C1049 ? (the ones used by the A1000 replacement MB). They are pretty inexpensive : $6.40 at digikey.
Keep in mind that 8MB of SRAM can suck up to 700mA - 1000mA of current on the 5V rail.
The A1000 replacement MB documentation gives some good hints for the RAM organization : 4 x 2MB banks, 4 chips per bank, each chip is for a byte lane, 4 chipselect have to be generated (one per bank), a 3-to-8 demux like a 74ACT138 can do that.

Regards,

Frederic

[rkauer]

Originally Posted by FrenchShark

Hello rkauer,

do you plan to use the CY7C1049 ? (the ones used by the A1000 replacement MB). They are pretty inexpensive : $6.40 at digikey.
Keep in mind that 8MB of SRAM can suck up to 700mA - 1000mA of current on the 5V rail.
The A1000 replacement MB documentation gives some good hints for the RAM organization : 4 x 2MB banks, 4 chips per bank, each chip is for a byte lane, 4 chipselect have to be generated (one per bank), a 3-to-8 demux like a 74ACT138 can do that.

Regards,
Frederic

Hi Fred.

I see all compatible 512kb x 8bits I can grab information for. My only concern is the final price for the 4Mb memory in the EC020 board (8 chips to make 4Mb x 6.40 = 53.20!!!). But I find some cheaper alternatives (not that cheap, BTW), like the 684000 (4.90 each at Futurlec, so 39.20!).

[rkauer]

For the current problem: not exactly a problem, if you source the power from the Floppy power connector, instead the on-board CPU clip.

[FrenchShark]

Originally Posted by rkauer

Hi Fred.

I see all compatible 512kb x 8bits I can grab information for. My only concern is the final price for the 4Mb memory in the EC020 board (8 chips to make 4Mb x 6.40 = 53.20!!!). But I find some cheaper alternatives (not that cheap, BTW), like the 684000 (4.90 each at Futurlec, so 39.20!).

How did you get this price ?
My search shows $8.40 per chip.
The best price I have seen is with the 3.3V version ($5.10 per chip) but it is not very practicle with a 5V part like 680x0 but, good for a FPGA project.
It is still a lot less expensive than the 8MB ZBT SSRAM I am using ($136 per chip !).
Maybe you should consider buying 32 chips and make 4 boards, parts are usually less expensive if you buy 25 or more.

Regards,

Frederic

[chiark]

Very, very interesting. From reading this thread it seems that the scope is somewhat creeping: is it possible to fix exactly what is a must have and design from there? Additions could come once the basics are in place.

I'd dearly love to see something out of this. I've just got a 600HD (8 quid! yay!) and would love some 020 goodness for it. Or preferably 030 goodness

[Zetr0]

@chiark

I believe the initial design is for an A600: 020 with upto 8mb of fast ram,

the second is to re-work this for the A500: with 020 +fast +IDE

the third inplementation will include (hopefully) an 030 with clockports

the 030 only has a couple of more signals than that of the 020, from this its possible to generate them using simple logic.

I am praying to get time and develop a signal map and signal generation list, this will help the project (i think lol) or atleast give it a reference to look on.

The trick at the moment is the memory handling, when i get some time (which seems like never this last week) I will review some of the SDR handling techniques that Oli_HD put up with a little hope i beleive i can help build a memory controller, rather than just a dumb blaster to the 8mb zorro config space.... AND should be able to get upto 512MB that would be something....

But again the initial design will be 020 + fast ram, of which will prolly be soldered to the board LOL

[Fingerlickin_B]

Quite a bit of jargon being thrown about that I don't understand, but I'm loving this thread...I feel like I'm learning whilst yearning for this project to come to life!

PZ.