Vampire 500 project started

[majsta]

@lukassid I m not familiar with anything I am learning and solving problems in process of creation. Vampire 600 is finished 99% but it is not stable, and this part of the design is almost the same like on Vampire500 so there is no harm done trying to work on this design because i will end up with same problems with stability. I know what I m doing don't worry

[pandy71]

Originally Posted by lukassid

Forgive me majsta but instead of finishing A600 project you started A500 accelerator, clearly not being even familiar with this Amiga. Can I ask why?

He doing me favour - i have no A600 (working yet) but i have A500 [sarcasm mode off] - there is no difference between A600 and A500 - so familiarity more or less for Majsta project is related to difference between PLCC and DIP sockets (ok this is also not fully true as Gayle in A600 is more advanced than Gary in A500).

http://eab.abime.net/735470-post90.html

Thank You zefrench!

[majsta]

I have gayle documentations but this doesn't help me because of my code. It could be easy if I m working with real CPU but working with TG68 takes different approach. So there is not much I can do until I found information's I need. I need Toni or someone else who understand all of this better than me to explain to me what needs to be done. TG68 somehow blocks that specific space so that is why I need more information's. It is not because something is wrong in TG68 it is because something else.

For example when you detect DE1000 space what happens next based on read and writes cycles of CPU.

Those are the parts of the code for IDE

IDE_CS1 <= '0' when (cpu_addr(14) = '0' and cpu_addr(13) = '0' and cpu_addr(12) = '0' and iASn = '0') or -- 8 bit
(cpu_addr(14) = '0' and cpu_addr(13) = '1' and cpu_addr(12) = '0' and iASn = '0') else '1'; -- 16 bit

IDE_CS2 <= '0' when (cpu_addr(14) = '0' and cpu_addr(13) = '0' and cpu_addr(12) = '1' and iASn = '0') or -- 8 bit
(cpu_addr(14) = '0' and cpu_addr(13) = '1' and cpu_addr(12) = '1' and iASn = '0') else '1'; -- 16 bit


IDE_select <= '1' when cpu_addr(23 downto 16)="11011110" else '0'; -- $DA0000 - $DA7FFF
OVR <= '0' when IDE_select = '1' else '1';

DTACK <= '0' when iTG68_DTACKn = '0' or IDE_select = '1' else '1';

GAYLE_ID <= '1' when cpu_addr(23 downto 16) = X"DE" else '0';


INTREQ <= '1' when cpu_addr(23 downto 12) = "110110101001" else '0'; -- $DA9xxx
INTENA <= '1' when cpu_addr(23 downto 12) = "110110101010" else '0'; -- $DAAxxx

So this is only preparation for the code and it is done for 10 minutes. It is without INT2 and any gayle identification. External DTACK is generated when OVR is activated. And IORD and IOWR are behaves like this.

..
when readS3 =>

if amiga_fallingedge_read='1' then -- Entering S3...
if IDE_select = '1' then
IORD <= '0';
end if;
mystate<=readS4;
end if;


when writeS5 => -- Nothing happens during S5
if amiga_fallingedge_write='1' then
if IDE_select = '1' then
IOWR <= '0';
end if;
mystate<=writeS6;
end if;

@Toni please take one step down and trust me when I say that I m idiot and tell me what to do

"Never argue with an idiot he will bring you down to his level and win from experience"

[pandy71]

Originally Posted by majsta

TG68 somehow blocks that specific space so that is why I need more information's. It is not because something is wrong in TG68 it is because something else.

Bus cycle for Gary when accessing this space ? - is bus is correctly terminated (DTACK?) - Gayle simply support more and perhaps all bus cycles are terminated in correct way - Gary is simple glue logic - A1000 cleaned - perhaps A1000 schematics can help.

http://www.devili.iki.fi/mirrors/hay.../docs/gary.txt

.sh 2 "Data Transfer Acknowledge (/DTACK)"
.pp
This signal is logically associated with the 68000's Data Transfer
Acknowledge input.  Normally in the Amiga system, Amiga system logic
creates /DTACK for a simple, no-wait state cycle (this may be varied by
the custom chips).  Therefore, this signal is treated as an output to
the Expansion and Coprocessor Slots, for most situations.  Any slow device on
the bus that needs to control /DTACK may do so by negating XRDY to hold off
/DTACK or asserting /OVR very quickly to tri-state /DTACK.  Note that
depending upon when /AS is asserted by a bus master when accessing the CHIP
memory, one of two possible cycles may result.  If /AS is asserted during C1
low, C3 low, the bus cycle is considered "in-sync", and will proceed, with 
/DTACK driven as for a normal, 4 tick clock cycle.  If instead, /AS is
asserted during C1 high , C3 high, the bus cycle is considered "out of sync"
and the internally generated /DTACK will be held off, causing a wait state
that's designed to "sync-up" the DMA cycle with the custom chip's memory
cycle.  This signal is on pin 66.

http://www.ianstedman.co.uk/downloads/Zorro2-pins.txt

[Toni Wilen]

Originally Posted by majsta

@Toni please take one step down and trust me when I say that I m idiot and tell me what to do

Sorry, this is not about Amiga hardware anymore, not my area of expertise

[robinsonb5]

A few comments off the top of my head - I don't have time to read up on Gayle right now, unfortunately.

Originally Posted by majsta

IDE_CS1 <= '0' when (cpu_addr(14) = '0' and cpu_addr(13) = '0' and cpu_addr(12) = '0' and iASn = '0') or -- 8 bit
(cpu_addr(14) = '0' and cpu_addr(13) = '1' and cpu_addr(12) = '0' and iASn = '0') else '1'; -- 16 bit

IDE_CS2 <= '0' when (cpu_addr(14) = '0' and cpu_addr(13) = '0' and cpu_addr(12) = '1' and iASn = '0') or -- 8 bit
(cpu_addr(14) = '0' and cpu_addr(13) = '1' and cpu_addr(12) = '1' and iASn = '0') else '1'; -- 16 bit

You should be treating your Gayle implementation like the Fast RAM implementation - not telling the motherboard anything about it - so you probably don't want iASn included in those. You'll want a new path through the state machine for Gayle. Note, that code does incomplete address decoding, so will also assert CS1 and CS2 for any Chip RAM accesses that happen to match on address bits 14, 13 and 12. If you replace "iASn='0'" with "IDE_select='1'" you'll be closer to what you want, I think.

IDE_select <= '1' when cpu_addr(23 downto 16)="11011110" else '0'; -- $DA0000 - $DA7FFF

"11011110" is 0xDE, not 0xDA. I'd recomment expressing address decoding in Hexadecimal, though - it's easier to debug!
i.e.: when cpu_addr(23 downto 16)=X"DA";
(You need to have a multiple of 8 bits in the comparison, though.)

OVR <= '0' when IDE_select = '1' else '1';

I'm reasonably sure you can actually ignore /OVR provided you don't tell the Amiga motherboard about Gayle accesses. (There's really no need for it to know, since Gayle can't do DMA.)

DTACK <= '0' when iTG68_DTACKn = '0' or IDE_select = '1' else '1';

Hmmm, not sure what your intention is there - but that will effectively make Gayle accesses terminate immediately - you need to do the opposite, make sure that the access waits for the IDE device. (That's what OVR is for, but like I said, there's no point involving the motherboard in IDE transactions. All you should need to do in your state machine is make sure cpu_ena remains zero until the access is complete.)

GAYLE_ID <= '1' when cpu_addr(23 downto 16) = X"DE" else '0';

Ah - you're using Hex notation there - good!

INTREQ <= '1' when cpu_addr(23 downto 12) = "110110101001" else '0'; -- $DA9xxx
INTENA <= '1' when cpu_addr(23 downto 12) = "110110101010" else '0'; -- $DAAxxx

That looks OK at a quick glance.

[majsta]

Hi
With iASn I wanted to make sure that CS1 and CS2 will be executed in read/write state machine, without that CS1 and CS2 will not be in synch with 7Mhz state machine. Actually CS1 and CS2 should start little earlier than AS is driven low so this is not quite correct but it is easy to fix.
Better choice and then everything in order will be like this.

IDE_CS1 <= '0' when (cpu_addr(14) = '0' and cpu_addr(13) = '0' and cpu_addr(12) = '0' and (mystate=readS1 or mystate=readS2 or mystate=readS3 or mystate=writeS1 or mystate=writeS2 or mystate=writeS3) else '1';-- 8 bit

Now everything is in order but then again I m not satisfied how this is done in gayle manual because it leaves possibility to have those cpu_addr detected in some other range but like I said investigation of this is easy and few minutes to do.

If I don't assert /OVR like this Gary prohibits decoding so TG68 can't read or write on that address, instead Tg68 detects "01" state.

Those hex or bin settings all was in hex but since I was thinking that something is wrong I have changed them for better visual understanding and maybe I didn't set them all correctly but I have changed so many things to discover problem.

And I can't threat Gayle like fast mem access because like I said TG68 doesn't see that space.

[pandy71]

Originally Posted by majsta

If I don't assert /OVR like this Gary prohibits decoding so TG68 can't read or write on that address, instead Tg68 detects "01" state.

And I can't threat Gayle like fast mem access because like I said TG68 doesn't see that space.

This is strange - Gary documentation says that all access are seen by Gary as FastMem Access and Gary provide full bus cycle termination except few mentioned areas which are different (mostly CHIP ram and RGA).

[majsta]

Yes strange situation but I m getting somewhere, it is easy for real CPU but in my codes is much harder because TG68 is paused most of the time. So basically I need to create some counters and according to them insert appropriate instruction.

Parts of the code looks like this now and i think that this could work with minor tweaks.

process(reset_a,sysclk) is
begin
if reset_a = '0' or gayle_id = '0' then
gayle_counter <= "000";
elsif gayle_counter = "101" and gayle_id = '1' then
gayle_counter <= "000";
elsif rising_edge(sysclk) then
if amiga_risingedge_read = '1' and gayle_id = '1' then
gayle_counter <= gayle_counter + 1;
end if;
end if;
end process;

this is counter.

So according to that counter D0 instruction should be executed and it goes something like this.

if gayle_counter = "001" then
ioTG68_DATA(15) <= '1';
mystate<=delay1;
elsif gayle_counter = "010" then
ioTG68_DATA(15) <= '1';
mystate<=delay1;
elsif gayle_counter = "011" then
ioTG68_DATA(15) <= '0';
mystate<=delay1;
elsif gayle_counter = "100" then
ioTG68_DATA(15) <= '1';
mystate<=delay1;
else
ioTG68_DATA(15) <= '0';
mystate<=delay1;
end if;

This is the principle but like I said need more tweaks. There are the chances that this should work.

[robinsonb5]

Originally Posted by majsta

This is the principle but like I said need more tweaks. There are the chances that this should work.

You're on the right track - but you need to reset your counter when the CPU writes to the Gayle ID register. You're currently resetting it on any access to anything *other* than the Gayle ID register, which won't work because the CPU fetches instructions from the Kickstart during the Gayle detection process.

Also, you should write the data to cpu_datain, not ioTG68Data. It's the CPU that reads the ID, not the motherboard.

The simplest way to implement Gayle ID would be as a serial shift register, something like this:

signal gayle_id_reg : std_logic_vector(7 downto 0);
....
if gayle_id='1' then
  if cpu_r_w='0' then -- Write cycle, so reset the ID
    gayle_id_reg<=X"d0";
  else
    cpu_datain(15)<=gayle_id_reg(7);
    gayle_id_reg<=gayle_id_reg(6 downto 0)&'0';  -- Shift register contents one bit to the left
  end if;
  mystate<=delay1;
end if;

[majsta]

I did it few hours ago and those are those "few tweaks". I think that this is working now.




Code looks like this now.
Counter.

process(reset_a,sysclk) is
begin
if reset_a = '0' or GAYLE_ID = '0' or (GAYLE_ID = '1' and cpu_r_w='0') then
gayle_counter <= "0000";
elsif gayle_counter = "1010" then
gayle_counter <= "0000";
elsif rising_edge(sysclk) then
if GAYLE_ID = '1' then
gayle_counter <= gayle_counter + 1;
end if;
end if;
end process;

when gaylelogicS0 =>

U4_1DIR_C <= '1';
U4_1OE_C <= '0'; -- enable ALVC => DATA
U4_2DIR_C <= '1';
U4_2OE_C <= '0';

if amiga_risingedge_read = '1' then
if gayle_counter = "0000" then
ioTG68_DATA(15) <= '1';
mystate<=gaylelogicS0;


elsif gayle_counter = "0001" then
ioTG68_DATA(15) <= '1';
mystate<=gaylelogicS0;

elsif gayle_counter = "0010" then
ioTG68_DATA(15) <= '0';
mystate<=gaylelogicS0;

elsif gayle_counter = "0011" then
ioTG68_DATA(15) <= '1';
mystate<=gaylelogicS0;

elsif gayle_counter = "0100" then
ioTG68_DATA(15) <= '0';
mystate<=gaylelogicS0;

elsif gayle_counter = "0101" then
ioTG68_DATA(15) <= '0';
mystate<=gaylelogicS0;

elsif gayle_counter = "0110" then
ioTG68_DATA(15) <= '0';
mystate<=gaylelogicS0;

elsif gayle_counter = "0111" then
ioTG68_DATA(15) <= '0';
mystate<=gaylelogicS0;

elsif gayle_counter = "1000" then
U4_1DIR_C <= '0';
U4_1OE_C <= '0'; -- enable ALVC => DATA
U4_2DIR_C <= '0';
U4_2OE_C <= '0';
mystate<=delay1;
end if;
end if;

So when all is done regarding Gayle ID CPU starts normal bus cycles. It all looks fine to me now regarding signals. Oh my god i just realized what you said about who reads ID, if that's true I could implement everything in few minutes instead I was trying to sync everything with motherboard because of kickstart. Damn.

[ajack]

Any updates on the Vampire 500?

[wawa]

http://www.majsta.com/

[majsta]

project was put on hold since imagine I didn't had A500 keyboard to perform some tests I wanted
Problem was with IDE controller and it seems to me that I didn't design it properly in hardware part

[Vot]

Are you guys working on 020+ compatibility. Im drooling waiting for an a1200 version.

[Don_Adan]

Here is doc for Gayle A600/A1200"
https://raw.githubusercontent.com/rk...inimig/Gayle.v

[majsta]

I know about that Gayle.v but like I said I designed hardware part wrong, my code works but until I found a A500 keyboard and redesign complete accelerator nothing can be done.

[Don_Adan]

Originally Posted by majsta

I know about that Gayle.v but like I said I designed hardware part wrong, my code works but until I found a A500 keyboard and redesign complete accelerator nothing can be done.

I can give you A500 keyboard, if you want. This keyboard has cutted connector (was connected directly to A1200).

; A4000 Gayle version

AT_Data EQU $00 ; 16/32 bit wide port
AT_Error EQU $06 ; error register
AT_SectorCnt EQU $0a ; # of sectors, 0 = 256
AT_SectorNum EQU $0e ; sector to start (1-based!)
AT_CylLow EQU $12 ; low byte of Cylinder number
AT_CylHigh EQU $16 ; high byte
AT_DriveHead EQU $1a ; Drive and head number | $A0
AT_Status EQU $1e ; (read) status reg, clears interrupt
AT_Command EQU $1e ; (write) command value, starts it
AT_AltStatus EQU $101a ; (read) alt status, doesn't clear int
AT_DeviceCtrl EQU $101a ; (write) device control - int/reset
AT_DriveAddress EQU $101e ; not used (pc-ish)
AT_IntStatus EQU $1000 ; interrupt status bit, active HIGH
; LONGWORD, in bit 31
AT_ModeReg0 EQU -$1000 ; Mode register 0 (bit 31!?)
AT_ModeReg1 EQU (-$1000)+2 ; Mode register 1 (bit 31!?)

[majsta]

http://majsta.com/modules.php?name=N...rder=0&thold=0

[NMI]

Fantastic! This is excellent news, I really want one of those in my A500.