16 February 2024, 08:55 | #21 |
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If aligment of source and destination is different then I would recommend to align the destination to long. So if the cpu has a data cache and the source is cachable the source misaligment can be mitigated by the cache.
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22 February 2024, 08:49 | #22 |
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Join Date: Jan 2012
Location: USA
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Movep.l ends up being a bit slower. 48 cycles for each pair of movep.l instructions. Same as four move.b (ao)+,(a1)+ instructions except using movep.l code still needs more time to get shifted bytes back into memory.
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