Terrible Fire Accelerators

BTW, I got 2 boards running now with CF and RAM, woot!

It's sketchy in an A2000 at 50MHz (hangs, crashes, graphics corruption), but works great at lower speeds.
I'll probably start tinkering with S4MASK delays to see if that helps.

FWIW, I modified xc3sprog (http://xc3sprog.sourceforge.net) with the Digilent hw programmer on Ubuntu 17.04 since I couldn't get the Xilinx tools to work properly.

@plasmab, have you tried adding stronger pull-ups on DTACK as a workaround for timing issues?

[TimT]

Yes 64 bit with windows 7, Random crashing with windows 10. are the files current for the TF530 rev3 on github? I have been using the guide in the Wiki.


"

• Open up 'ISE iMPACT' and double-click 'Boundary Scan' in the iMPACT Flows pane.
• Right click the appropriate CPLDs and select the respective firmware JED's from the "

when I open impact and double click boundary scan there are no clpd's to right click. I can only initialize chain to get the cpld's to show up. if I try to load a .jed file I get error parsing jedec file at line 518. Impact seems to communicate with the cpld's just fine, just can't seem to assign any files to them. uploading some images to show the errors.


Thanks

[plasmab]

Originally Posted by TimT

Yes 64 bit with windows 7, Random crashing with windows 10. are the files current for the TF530 rev3 on github? I have been using the guide in the Wiki.


"

• Open up 'ISE iMPACT' and double-click 'Boundary Scan' in the iMPACT Flows pane.
• Right click the appropriate CPLDs and select the respective firmware JED's from the "

when I open impact and double click boundary scan there are no clpd's to right click. I can only initialize chain to get the cpld's to show up. if I try to load a .jed file I get error parsing jedec file at line 518. Impact seems to communicate with the cpld's just fine, just can't seem to assign any files to them. uploading some images to show the errors.


Thanks

I've never seen that ever. Seen programming error occasionally but not what you are seeing.. can you check your jed file isnt corrupted or something weird.

EDIT: that isnt even managing to load the jedec file.. I would bet you have downloaded it from github incorrectly and its got html headers in it.

[supaduper]

With my knock off xillinx programmer I use version 14.7 of xillinx software on win 8, had to do the file hacks as described in the wiki, so if you can try ver14.7 of impact

[plasmab]

If when you open your jed file with a text editor it looks like this ...



Then you screwed up downloading the Jed file. You can’t right click save as with GitHub.

[TimT]

Yes, That's what I did right click/save as, I did not know it would do that. download the correct way and was able to program the chips. anyone know what version kickstart I need to boot the board? I got a feeling I will be upgrading as my A500 has kickstart 1.2

Thanks everyone for the help!

[LADmachining]

My TF530 has been completed, and during testing with DiagROM, all I see on the serial terminal are the symbols '<>' when powered-up, then no other output.

The serial link has been tested, and works fine with a 68000 installed in the socket, so it seems there are issues with my '530.

I have spent the last couple of hours re-checking the CPLD pins, and carrying-out point-to-point continuity checks, which don't reveal any issues. Resistance checks between address bus and data bus lines are also good (no shorts). No FPU has been installed thus far.

Waiting for another '030 to arrive so I can try that. Any other advice in the mean-time would be appreciated.

[plasmab]

Originally Posted by LADmachining

My TF530 has been completed, and during testing with DiagROM, all I see on the serial terminal are the symbols '<>' when powered-up, then no other output.

The serial link has been tested, and works fine with a 68000 installed in the socket, so it seems there are issues with my '530.

I have spent the last couple of hours re-checking the CPLD pins, and carrying-out point-to-point continuity checks, which don't reveal any issues. Resistance checks between address bus and data bus lines are also good (no shorts). No FPU has been installed thus far.

Waiting for another '030 to arrive so I can try that. Any other advice in the mean-time would be appreciated.

Check AS20 goes low (FPU is best place to check), then check AS goes low, then DTACK and DS20 in that order. I’d bet on a data bus short or address bus short.

[LADmachining]

Originally Posted by plasmab

Check AS20 goes low (FPU is best place to check), then check AS goes low, then DTACK and DS20 in that order. I’d bet on a data bus short or address bus short.

Will dig the logic analyser out and check that first.

[plasmab]

I now have a second terminally ill close family member, a new job and a bunch of friends have either died or also have terminal illnesses.

All my Amiga stuff is packed away and my thoughts are elsewhere

[EzdineG]

Originally Posted by plasmab

I now have a second terminally ill close family member, a new job and a bunch of friends have either died or also have terminal illnesses.

All my Amiga stuff is packed away and my thoughts are elsewhere

Sorry to hear this. If you need to talk or just blow off steam don’t hesitate to holler.

[pgovotsos]

Originally Posted by plasmab

I now have a second terminally ill close family member, a new job and a bunch of friends have either died or also have terminal illnesses.

All my Amiga stuff is packed away and my thoughts are elsewhere

Very sorry to hear that. Of course family is a much higher priority than any of this stuff. My prayers for you and your family.

[keith]

I am really sorry to hear that.

[shaf]

I can sympathize as i've been through the same thing myself. My thoughts are with you.

Is Impact supposed to identify the XC9572XL's? I get the circuit showing up with two unidentified chips but can't program them. I'm using a chinese programmer which is detected in 14.7/windows 10.

[solidcore]

@Plasmab sorry to hear about further dreadful news.

Originally Posted by the_master

Is Impact supposed to identify the XC9572XL's? I get the circuit showing up with two unidentified chips but can't program them. I'm using a chinese programmer which is detected in 14.7/windows 10.

Open your .jed files and make sure they're not the .html download common problem when downloading files from Github as Stephen has suggested previously. If they are the jeds, it's unusual for them not to program unless fake chinese chips, bad programmer, or bad connection/bridges/ or lack of solder on a pin, microscope/jewelers lens time and double check your jtag header.

Originally Posted by solidcore

@Plasmab sorry to hear about further dreadful news.



Open your .jed files and make sure they're not the .html download common problem when downloading files from Github as Stephen has suggested previously. If they are the jeds, it's unusual for them not to program unless fake chinese chips, bad programmer, or bad connection/bridges/ or lack of solder on a pin, microscope/jewelers lens time and double check your jtag header.

Yeah I had a bit of a read through this thread and did check the files before posting, they are fine. I have 4 A500s and have built 3 of the TF530s, I planed to build 4 but had trouble finding some parts (mostly the 1k resistor arrays). So should the Xilinxs be detected and named in Impact when you do the boundary scan? because that's the part I'm not sure of what it should look like. I really should have saved the relevant build videos before they were all deleted, I had a feeling he was going to do that, was stupid of me not to save them. I've had these boards boards built for a while but was waiting on the programmer and being able to download the software (I had to fake out an address to get that). I used a jewelers lens to build them, I'm 100% sure there's no soldering errors, the Xilinxs could be fake if there's such a thing but I had two lots from two different sellers.

[chue]

Yes, Impact should ID the chips. You should see two chips with "xc9572xl bypass".

Originally Posted by chue

Yes, Impact should ID the chips. You should see two chips with "xc9572xl bypass".

Thanks, ok I'm not seeing that. Rather than get down and out about my defeat to program them. I'm building 3 new boards. This time I'll get the xilinxs from a known good source and program them before I complete the boards. I will return when I either fail again or succeed to let you know .

[solidcore]

Originally Posted by the_master

Thanks, ok I'm not seeing that. Rather than get down and out about my defeat to program them. I'm building 3 new boards. This time I'll get the xilinxs from a known good source and program them before I complete the boards. I will return when I either fail again or succeed to let you know .

Genuine parts from : RS-Online, Digikey, Mouser, and possibly quite a few others.

Fake parts from : Ebay (Depends on Seller/source), UTSource and other chinese sources. I think most of us can generally say utsource has proven time again to reward us with fake items and is no longer worth it. Perhaps for the obsolete items when you have no choice China may be worth taking the risk, but otherwise if you are a hardware dev then just change the design to accommodate. Unfortunately for DIY enthusiasts BGA is replacing QFN and so on, and as chips become more complex in design and offer more I/O we'll all need to adapt to BGA packages, some will buy re-flow ovens, others will pay China do all the hard work for them but that doesn't come without risks.