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Old 23 February 2018, 23:03   #201
Chucky
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bahh skip those big vias too mucgh work. maybe implement Mathesar DS1100Z-25 on the board instead.. YUP! that will be done..
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Old 23 February 2018, 23:34   #202
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Re new vias, I was thinking that was going to be a big job. Just as easy to solder wires to the ic pads anyway for prototyping.
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Old 23 February 2018, 23:44   #203
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yup.. so soon I have made a place for the delayline aswell..
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Old 24 February 2018, 00:11   #204
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Well did some modifications.. hope they are ok.. should be
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Old 24 February 2018, 00:27   #205
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That looks great, Chucky!
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Old 24 February 2018, 00:41   #206
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As I haven't tested this yet (just did it.. ) this download will be on YOUR risc.

I will order some PCBs when I am done with the devboard for my Rev2 project..


http://www.hertell.nu/webfiles/A3660Rev11.zip
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Old 24 February 2018, 08:36   #207
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Quote:
Originally Posted by Chucky View Post
As I haven't tested this yet (just did it.. ) this download will be on YOUR risc.

I will order some PCBs when I am done with the devboard for my Rev2 project..


http://www.hertell.nu/webfiles/A3660Rev11.zip
Many thanks for this Can't wait to order and build this

I checked the changes by overlaying the gerber files and found a small error on the top layer near C204, see attached picture.
All the other changes on top and bottom seem correct to me but I didn't check the inner layers as the offsets are different and Viewmate doesn't like that for the inner layers.

EDIT: forgot what I said, the error was in rev1.0!!!! Rev 1.1 is OK
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Old 24 February 2018, 08:39   #208
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oh I had that reported. didn't I fix it.. bah! will do after breakfast
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Old 24 February 2018, 08:48   #209
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Ok, got the inner layers working into viewmate now, the VCC pin of the DS1100Z seems not connected to the power plane (layer 3).

PS my breakfast was at 7:00AM!
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Old 24 February 2018, 08:56   #210
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weiird.. checked in sprint..


edit: ahh not so weird. as it is a trace to the cap that feeds the delayline aswell... so. it is ok
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Old 24 February 2018, 09:05   #211
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Quote:
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weiird.. checked in sprint..


edit: ahh not so weird. as it is a trace to the cap that feeds the delayline aswell... so. it is ok
Check, I see it as well. Sorry for all the false alarms. I guess I was not fully awake yet .

I will also order a batch of PCB's this weekend. My A3000 has been without a 060 for far too long now.

Thanks again for this wonderful project!
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Old 24 February 2018, 09:06   #212
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Well next step is to get this CoreEP3C16 FPGA devboard to a A3660 Rev2 devboard working and move all old shit to that one (NO cpu will still be a real one!) and add some memory and stuff..

so time to do serious pcb cadding (in eagle) so I can order those..
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Old 24 February 2018, 13:42   #213
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Quote:
Originally Posted by Chucky View Post
Well next step is to get this CoreEP3C16 FPGA devboard to a A3660 Rev2 devboard working and move all old shit to that one (NO cpu will still be a real one!) and add some memory and stuff..

so time to do serious pcb cadding (in eagle) so I can order those..
Have you also considered using KiCad? I find KiCad easier to work with than Eagle and the 3D viewer is quite handy to see what the final board will look like.

The Altera chips are nice, how are you going to handle the 3V3/5V level shifting? I guess it will be easy with a 68060 CPU as that one is 3V3 anyway. Than you only have to convert the signals coming from the motherboard. I was looking at this project on Github:
https://github.com/ezrec/galpal
It can convert jedec files into a verilog model. If it works you can just clone the whole thing into an FPGA wihout coding! (Of course you still need to do some hard work to add memory, it will probably be a whole new design then)

We need more people like you and PlasmaB. Closed source Amiga's are no longer the way to go. For example, the Amy board looks like incredible fun: http://eab.abime.net/showthread.php?t=90771
But why did they not open up the sources
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Old 24 February 2018, 13:57   #214
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I have looked at the TXB0108 autosensing levelshifters..
and to replace the old buffers I will use 74LVCH162245 so internnaly on the board. everything will be fully 3.3V

kicad.. yes.. I will move there someday. but I decided to do the devpcb in eagle. then when I do the final product.. it will be done in kicad.
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Old 24 February 2018, 15:00   #215
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TXB0108 is meant for push-pull CMOS, not open drain. It might work but it's going to affect the propagation delay.
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Old 24 February 2018, 15:19   #216
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Bah.. so somewhat "back to drawingboard"
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Old 16 March 2018, 18:13   #217
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Today PCBs arrived.


I also got my Experimental PCB:

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Old 16 March 2018, 19:13   #218
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Awesome!
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Old 16 March 2018, 20:28   #219
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Beautiful!!!!

Do you have any of those rev1.1 boards for sale? I'm interested!
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Old 16 March 2018, 20:39   #220
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Awesome! Kickin Rad!
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