21 May 2024, 20:16 | #4601 |
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Yes. Take Aga bus, you have a peak rate at 28 mb. So if you Have
- One chip-ram bus - One bus for trap door ram (without bitplane penalties) - one for HW Registers (64 bit transfer rate possible!) - One for Fast-mem Even without adding expensive ram, you'll have a peak rate at 28mb*4 = 112mb! This, with a few more pennies.. These are just fixes Last edited by sandruzzo; 21 May 2024 at 20:24. |
21 May 2024, 20:33 | #4602 | ||||||
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There is no such thing.
That is by no means a bus. Quote:
Like a speed of 4 km? Or a electric power of 3 amp? Quote:
Quote:
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A hardware register bus? What is that supposed to be? Please get your terminology right - it is really hard to figure out, what you are actually talking about - in this case I have seriously no clue. Quote:
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You seem to miss the basic understanding of buses, memory access and frankly all the rest. |
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21 May 2024, 20:42 | #4603 |
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@Gorf
I miss some things, maybe my terms aren't ok. I was just wondering what would have been possible if they allowed the possibility to acce to HW register with double-cas(64it) ( maybe whitout bitplanes penalties) instead of 16 bit as the old OCS/ECS. fai una foto Last edited by sandruzzo; 21 May 2024 at 20:48. |
21 May 2024, 21:03 | #4604 |
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Pseudofast ram is "slow ram" and that was a cheap solution to essentially add (hypothetically a lot more) memory by hooking additional RAM to CHIP RAM addressing and refresh signals... Downside was... it was damn slow (hence the name).
You cannot just add new buses - you need to route new signals and create new controller inside ASIC. And Commodore was hardly able to do things like Agnus and Alice. So ... no go. Also - that'd fragment memory even more and you'd have to handle that as a developer... |
21 May 2024, 21:10 | #4605 |
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@Promilus
No question about it, but it could have opened a lot of opportunities. They could have the exact same cycles as main bus and synchronization(226/7 slots), but just with more spare cicles for both chipset(but not bitplanes) and cpu |
21 May 2024, 21:22 | #4606 | |
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Quote:
http://amigadev.elowar.com/read/ADCD.../node0011.html Most of them will only take a 16bit value and only NEED 16bit or even less! You don't want to read 64 bit of joystick data at once, when all the information comfortably fits into 16bit. There are only very few registers that would profit from a 32bit wide access, like eg. the colour registers, which now need 2 accesses instead of one ... Almost no registers would profit from 64bit (DoubleCAS) That said: Paula's AUDx and Floppy DMA could theoretically profit from wider access, but this would need an internal redesign of Paula ... we talked about that many times already in this thread. A much simpler solution would have been second Paula in parallel for an other 4 sound channels and the DMA map shows there would have been enough room for that as there is an CPU cycle between each audio DMA fetch: So by changing into "nasty" mode and blocking the CPU these slots could have been used to drive a second Paula - with only rather small changes in Agnus/Alice and no changes to Paula. |
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21 May 2024, 21:37 | #4607 | |
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Quote:
Problem is related to fixed DMA slot allocation - trade of between simplification of state machine and some design goals. AGA could be different introducing twice faster chipset bus and offering new DMA dynamic slots while still offering old, static DMA slot allocation to keep legacy compatibility... AGA could offer this but CBM ignored opportunity. But nevertheless Paula at 56kHz works well so it shows that some room for improvements was possible (same like adding ADPCM decoder to Paula efficiently doubling sample rate and bit depth so 16 bit at 56kHz without any change in DMA slots). |
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21 May 2024, 21:41 | #4608 |
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@Gorf
Think about an Aga Copper than could load 4 16bit registers at once... |
21 May 2024, 21:52 | #4609 |
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21 May 2024, 21:55 | #4610 |
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21 May 2024, 21:57 | #4611 |
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21 May 2024, 22:08 | #4612 |
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Let me see:
lea.l $dff000,a5 move.l #$09f00000,bltcon0(a5) ; load bltcon0/1 . 2 16 bit registers What prent it to be 2 registers at once? bus... If cpu can so could have been done by Copper |
21 May 2024, 22:42 | #4613 | |
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Quote:
There is not really not much performance gain to expect on this front. Nice to have for some use cases but not a huge deal. And it would make Copper much more complicated, so it is not really easy to archive and it would potentially break compatibility with old copper lists ... you would need to set a different mode for "new Copperlist" and you need to be very careful not to be in the wrong Copper mode, if you only want to write a 16bit value ... At this point a totally different approach would be much more useful: A small memory (1-2 KB) inside of a Neo-Copper (like a programmable shader in todays gfx-cards).... |
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21 May 2024, 22:53 | #4614 |
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@Gorf
I think only 64 bit inside could suffice. With an "advance move", you could make Copper point to an address (a.k.a registers') and then store the values. With a 2 stage "copper" you could load and store values very fast, like the blitter does!. Not a big deal, for good engineers! Registers are nothing more than fast internal, ram! |
21 May 2024, 23:05 | #4615 | ||
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You want the value on the data-lines so Denise/Lisa or Paula can take that value and store it. That is the magic of copper-lists: the first word tells Agnus/Alice what value to put on the RGA bus, the following word is the data that is put directly from RAM into the registers chosen on the RGA... To change this you need to implement a lot of changes on every corner - that is equivalent to a complete redesign (they tried with AAA) Quote:
And at this point it would make more sense to leave the old Copper be as it is for compatibility and add something completely new in for advanced features. |
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22 May 2024, 04:06 | #4616 | |
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Lisa has 4X the Chip RAM bandwidth access when compared to ECS Denise. Lisa is capable of displaying 256 colors (8 bitplanes) in Double PAL/Double NTSC modes. ECS Denise in double scan resolution modes has reduced to 2 bitplanes i.e. 4 colors. Alice has 16-bit data pins. Alice's Blitter (2D object manipulator) remained in OCS/ECS's 16-bit x 3.5 Mhz. The Blitter can do very basic arithmetic math, but it's very primitive. Refer to 3DO's MADAM example. The original intent for AGA was to be bundled with $20 DSP3210 @ 50Mhz as the object manipulator upgrade. DSP3210 is equipped with a hardware barrel shifter beside the 12.7 MIPS (integer pipeline) and 25 MFLOPS FP32 (floating point pipeline) @ 50Mhz. AT&T marketed DSP3210 as "3D and multimedia DSP". Object manipulator switched from 2D to 3D. DSP3210's role in Amiga Hombre is taken over by the integrated custom PA-RISC @ 100 to 120 Mhz with 3D extensions. In 3DO, MADAM has custom 3D math hardware and a quadrilateral 3D texture mapper @ 25 Mhz. Motorola's CPU wasn't price-competitive with a 3D math power use case. 68030 wasn't modified with a fast integer math instruction subset (just a few ADD and MUL instructions moved from ROM'ed microcode to hardware implementation) like its hardware barrel shifter. There's less need for most 68K instruction set hardware implementations like 68040 when the platform specifically targets 3D-related math. The main difference between 68040 and 68030 is moving instructions from ROM'ed microcode to full hardware implementation at the cost of large-scale transistor usage i.e. 1.2 million transistors. 68882 wasn't designed for game 3D performance i.e. just above 1 MFLOPS @ 50Mhz Motorola didn't provide Intel-style drop-in RapidCAD (486DX without L1 cache) for 1st generation full 32-bit CPU socket. It's a 68040 infrastructure switch or bust. RapidCAD is Intel's fastest drop-in CPU for the 386DX socket infrastructure. There are 486DLC clones for 386DX socket infrastructure that exceeds AMD's 386DX-40. My Dataquest links show 68040's prices aren't following Intel 486 counterparts. 680EC040 is useless for the Amiga or any desktop 68K platforms. Last edited by hammer; 22 May 2024 at 04:15. |
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22 May 2024, 04:33 | #4617 | |
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Quote:
The Copper is less relevant for packed pixel color display with high memory bandwidth i.e. 1 byte (8-bit, 256 colors), 2 bytes (16-bit, 65,536 colors), and 3 bytes (24-bit, 16,777,216 colors). Modern GPUs have delta color compression/decompression, texture compression, and a large cache to conserve external memory bandwidth. Original Amiga team-led 3DO beats the Commodore Semiconductor Group's graphics/audio chipset efforts. Blame the soft drink CEO for dismantling the original Los Gatos Amiga team. The Copper induces complexity for mainstream game programmers i.e. it's easier on PC VGA. Last edited by hammer; 22 May 2024 at 04:38. |
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22 May 2024, 04:48 | #4618 |
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Copper is very important to prevent CPU overload. Let's do a real example: chunky-copper. On Aga you can get to 2x2, with copper like i stated, you can archive 1x1 like nothing! Like I told before, they already did it with Blitter: 2 stage chip that is very fast even though it is "primitive". Why is blitter on Aga faster than the same exact chip on ECS? Because you can feed it due to the fast bus, a.k.a you can load it almost at full rate, and blitter can store data into chip-mem faster!
You can even have a copper without any "registers" inside and do load and store at faster speeds like this: Load datas ---> Store Datas -------------------Load Datas ---> Store Datas ---------------------------------------Load Datas ----> Store Datas Not A Big Deal to do! |
22 May 2024, 04:57 | #4619 | ||
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Quote:
CD32 has additional audio paths from two 16-bit DAC CD-ROM and FMV module https://bigbookofamigahardware.com/b...2b5d29ffec.jpg. AA3000+ has additional 16-bit DACs via DSP3210 path. https://amitopia.com/updated-dsp-321...a-3000-is-out/ Quote:
A1200 was "PCJr'ed". |
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22 May 2024, 05:00 | #4620 | |
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AGA ChipRAM has less bandwidth contention, hence the same Biltter has up to 60% boost. Lisa has up to 4X (400 percent) performance boost which is mismatched with a 60 percent boosted Biltter. Chip RAM only 68EC020 (effectively 7 Mhz) is about 56% of AGA Biltter. There are reasons for CPUFastBilt patches with faster 68K CPUs i.e. the accelerator turned into de-accelerator. Commodore's Amiga chipset = the original de-accelerator, before S3. AGA Lisa and CPU's access to 32-bit Chip RAM is fine for displaying +50 fps 256 colors 320x200 Star Wars Dark Forces when the primary object manipulator is very fast. Last edited by hammer; 22 May 2024 at 05:10. |
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