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Old 04 October 2020, 13:19   #1
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Copper wait until end of scanline

Hi all,

Here's another copper related question. I have a 320x256 PAL setup. I'm trying to set BPLCON1 at the end of the scanline using the copper.
EDIT: Amiga 500 - 2 bitplanes. Enabled DMA channels bitplane and copper.

Here's a snippet from the copper list.
  dc.w  $4BDF, $FFFE  ; wait for vpos >= $4B and hpos >= $DE
  dc.w  $0102, $0000  ; BPLCON1
At the start of scanline $4B the copper reads the wait. I can see the two word instructions in the DMA debugger

Line: 4B  75 HPOS 00   0:
 [00   0]  [01   1]  [02   2]  [03   3]  [04   4]  [05   5]  [06   6]  [07   7] 
 COP  08C  RFS  1FE  COP  08C  RFS  1FE    CPU-RW  RFS  1FE                     
     4BDF      FFFF      FFFE      FFFF      01FF      FFFF                     
 0001D310            0001D312            0001D256                               
 580F8E00  580F9000  580F9200  580F9400  580F9600  580F9800  580F9A00  580F9C00
I would expect an extra bus cycle for the wait to hit at bus cycle $DE. However, that's not how the DMA debugger sees it.

Line: 4B  75 HPOS D8 216:
 [D8 216]  [D9 217]  [DA 218]  [DB 219]  [DC 220]  [DD 221]  [DE 222]  [DF 223] 
   CPU-RW              CPU-RW                                COP  08C           
     0240                01FF            W                       0102           
 0001D254            0001D256                                0001D314           
 58113E00  58114000  58114200  58114400  58114600  58114800  58114A00  58114C00 

 [E0 224]  [E1 225]  [E2 226] 
 COP  1FE  COP  102  RFS  03C 
 #   0066      0066      FFFF 
 0001D316  0001D316           
 58114E00  58115000  58115200
I can't make any reason out of it. It seems like the wait cycle is at $DC, if I understand the "W" correctly.

Then at $DE the instruction fetch for BPLCON1 happens, and it's set at $E1, which is not an even cycle - I thought the copper couldn't do that?

Sandwiched in between, at $E0, there is a mysterious copper no-op.

Finally at $E2 - what I thought would be the last copper cycle, is an RFS, which I guess is a memory refresh, but shouldn't that be at bus cycle -1?

In my mind, this should have played out like this:
  • $DE a wait cycle belonging to the previous wait
  • $E0 instruction fetch
  • $E2 set BPLCON1

Any help much appreciated

Last edited by Markowitch; 04 October 2020 at 14:17.
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Old 04 October 2020, 14:16   #2
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I guess you have other questions (some are on your post) so I will answer in advance (the $e0 slot is explained on above link).

What is the RFS -1 cycle?
The last of the previous line, therefore $E2 for PAL.

Why if I have a CWAIT at $DF the first valid fetch is a $DE?
Well, as you know the bit0 of the first instruction word of the copper defines if you have a MOVE or a WAIT(or SKIP),
so in practice you can have waits only for even positions for the video DMA slots.
The third cycle of the WAIT is before the requested slot (that is a good thing!) so the actual fetch for the new instruction is exactly on the required slot.

But if I set a WAIT at slot 0 of a certain line what is the previous slot?
This is a special case. There is not a previous slot for 0.
So in practice waiting for slot 0 or slot 2 of a certain line has the same effect.

I think with all this information your questions concerning the distribution of DMA slots for copper is fully answered.

Last edited by ross; 04 October 2020 at 15:34.
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Old 04 October 2020, 15:41   #3
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Thanks Ross
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