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Old 27 May 2019, 02:37   #1
Kai
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14Mhz Accelerator

And yet another post from me

This is a re-do of the 14Mhz accelerator from Livio Plos - not my schematic, just re-doing it in KiCad like the FastRAM project.

This is a 100% through hole project as per my FastRAM board, for the same reasons. PCB's should be relatively cheap, i'm having a few made at PCBWay this coming week (roll on payday!).

It's designed for PLCC 68HC000's, which come in higher speed grades than the DIP-64's, and are more abundant, run cooler and are just plain smaller.

Github is here: https://github.com/kr239/A500-14Mhz-Accelerator



Did I mention it stacks with the FastRAM board, too?

I may have to integrate this into the FastRAM board....and add IDE as well...
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Old 27 May 2019, 04:13   #2
Magic
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Nice! Thank you
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Old 27 May 2019, 14:02   #3
utri007
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Any one know it this works with CDTV? I really would like to get more power under the hood. Any one selling build units, I would like to buy one.
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Old 27 May 2019, 20:41   #4
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Nice. Thankyou. When I open the schematics in KiCAD, it complains about sheet 2 missing. Did you forget to upload it to github?
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Old 27 May 2019, 22:31   #5
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Big grin

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Originally Posted by jkp View Post
Nice. Thankyou. When I open the schematics in KiCAD, it complains about sheet 2 missing. Did you forget to upload it to github?
Good catch! Uploaded to github now - sorry! Was late when i did it...
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Old 28 May 2019, 08:30   #6
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@Kai

Great work.

I would suggest you add a note somewhere mentioning that a pure Amiga accelerator with no ram is like a racing car with flat tires: you are not taking advantage of its full potential. Just link that comment to the 8MB AutoConfig ram expansion you also redesigned to achieve a better overall performance.
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Old 02 June 2019, 14:30   #7
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Quote:
Originally Posted by Kai View Post
And yet another post from me

This is a re-do of the 14Mhz accelerator from Livio Plos - not my schematic, just re-doing it in KiCad like the FastRAM project.

This is a 100% through hole project as per my FastRAM board, for the same reasons. PCB's should be relatively cheap, i'm having a few made at PCBWay this coming week (roll on payday!).

It's designed for PLCC 68HC000's, which come in higher speed grades than the DIP-64's, and are more abundant, run cooler and are just plain smaller.

Github is here: https://github.com/kr239/A500-14Mhz-Accelerator

Did I mention it stacks with the FastRAM board, too?

I may have to integrate this into the FastRAM board....and add IDE as well...
Nice! I for one would like to build this. I like the fact the fact that the design does not need any programmable ic's. However, I think you need to improve the decoupling. There is only one 100nf cap for the 68hc000 and even that one has long, thin traces connecting it. The logic ic's have no caps at all! Especially with hcmos you need proper decoupling and grounding. As the design is now it might be very unstable.
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Old 02 June 2019, 14:33   #8
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Quote:
Originally Posted by gulliver View Post
@Kai

Great work.

I would suggest you add a note somewhere mentioning that a pure Amiga accelerator with no ram is like a racing car with flat tires: you are not taking advantage of its full potential. Just link that comment to the 8MB AutoConfig ram expansion you also redesigned to achieve a better overall performance.
True, but.... This is a nice and easy to built design which might give a stock 500 that little bit extra. Also, as long as it gives you a nice sysinfo comment:
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Old 02 June 2019, 17:02   #9
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I did think about that, i'll add some more decoupling caps and update the github later

I think i was just concerned with adapting the original 1993 schematic in KiCad first - before hacking it around.
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Old 02 June 2019, 19:40   #10
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Okay - updated with decoupling caps:



Schematic, gerbers etc all updated.

Rotated the PLCC socket and instantly it only required 23 via's once the routing was finished
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Old 03 June 2019, 00:07   #11
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As with my other projects, i'm putting direct links to them on PCBWay for anyone that wants to get some PCB's printed:

https://www.pcbway.com/project/share...00_models.html
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Old 03 June 2019, 20:32   #12
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Quote:
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Okay - updated with decoupling caps:

Schematic, gerbers etc all updated.

Rotated the PLCC socket and instantly it only required 23 via's once the routing was finished
You are quick! Are you using an autorouter? It would take me a few days to manually route a board like this. It seems like an autorouted board as the decoupling caps are not routed properly. The decoupling caps need to be very close to the IC's they are decoupling. On your board they are all in one place and connected via long, thin traces. This *can* work if you are using a 4-layer board (the all in one place part, not the long thin traces part, just look at the layout of the Terasic DE1 FPGA board for example) but with a 2-layer board decoupling is very critical. Also, you need proper ground connections (wide copper traces, copper pours). Autorouters are generally not good at this. I would say that this board would still behave unstable. I like your style though, the board does look very nice with it's 45deg angled edges

Last edited by Mathesar; 03 June 2019 at 21:05.
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Old 03 June 2019, 21:14   #13
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Lightbulb

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Originally Posted by Mathesar View Post
You are quick! Are you using an autorouter? It would take me a few days to manually route a board like this. It seems like an autorouted board as the decoupling caps are not routed properly. The decoupling caps need to be very close to the IC's they are decoupling. On your board they are all in one place and connected via long, thin traces. This *can* work if you are using a 4-layer board (the all in one place part, not the long thin traces part, just look at the layout of the Terasic DE2 FPGA board for example) but with a 2-layer board decoupling is very critical. Also, you need proper ground connections (wide copper traces, copper pours). Autorouters are generally not good at this. I would say that this board would still behave unstable. I like your style though, the board does look very nice with it's 45deg angled edges
Yep - using freerouter with KiCad - export the Specctra DSN, import into freerouter, let my R5-2600X plough through it, export the session file, re-import into KiCad.

Routing by hand would be something I dunno if i could manage - i'm poor on recreational time, and my dexterity isn't great, so it would be an exercise in frustration. I could do it as a 4 layer board, with top and bottom copper being ground planes, although that'd push the cost of the PCB up a lot more. I know KiCad has an option for copper pour/fill i could maybe try - from a quick test, it seems to look a lot better.

I think the issue with the autorouter is, it always takes the shortest route possible, to cut down on trace length. I let the routing run for a good hour as it tried to optimise it/remove vias/reduce trace length Routing isn't my strong suit - this is after all, just a 'during my lunchbreak' hobby

That being said, I'll try and take your advice and try out some new tricks in KiCad - while trying this, i had a go at copper fill:






Looks better?
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Old 03 June 2019, 21:14   #14
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The 45 degree corners are in no way influenced by the monitors and paper from Battlestar Galactica...and certainly not a reference to cutting corners in design
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Old 03 June 2019, 22:58   #15
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Quote:
Originally Posted by Mathesar View Post
The decoupling caps need to be very close to the IC's they are decoupling. Also, you need proper ground connections (wide copper traces, copper pours).
This ^



Alternatively, star power may help if wide traces aren't possible.
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Old 04 June 2019, 00:19   #16
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...star power?
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Old 04 June 2019, 12:11   #17
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...star power?

if you run e.g. single power/gnd traces around the board from chip to chip, you risk creating a big loop which is bad for EMI, and also may cause supply problems for chips along the (thin) trace since they will each cause a voltage drop so when you get to the last chip on the trace, the voltage could be too low to run the chip properly. 'Star' just means running traces out from some specific point so the power consumption of one chip doesn't affect others so much, and if you can run power and gnd close to each other on each side of the board, this also helps reduce radiation (because the power/gnd loop is small).
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Old 04 June 2019, 15:01   #18
Kai
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Quote:
Originally Posted by hooverphonique View Post
if you run e.g. single power/gnd traces around the board from chip to chip, you risk creating a big loop which is bad for EMI, and also may cause supply problems for chips along the (thin) trace since they will each cause a voltage drop so when you get to the last chip on the trace, the voltage could be too low to run the chip properly. 'Star' just means running traces out from some specific point so the power consumption of one chip doesn't affect others so much, and if you can run power and gnd close to each other on each side of the board, this also helps reduce radiation (because the power/gnd loop is small).
Hmm - interesting stuff - i wonder if there's an option in the board setup for that...
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Old 10 June 2019, 15:22   #19
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Here we go - decoupling caps placed better, and better copper fill: https://github.com/kr239/A500-14Mhz-Accelerator

And integrated into the 8MB FastRAM here:

https://github.com/kr239/A500-8MB-FastRAM/tree/v3



I had a very dull weekend...
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Old 22 June 2019, 21:56   #20
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Really great work here! I think IDE is not easy doing here or why have you excluded IDE ?
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