15 August 2018, 22:15 | #1 |
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GCR encoding
I wonder if any games used GCR encoding instead. The controller in Paula can apparently read/write this just fine so it might be an interesting thing to know.
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15 August 2018, 22:23 | #2 |
CaptainM68K-SPS France
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16 August 2018, 09:11 | #3 |
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Very unlikely (I don't trust any rumors as usual) because it requires them to be undumped. UAE does not have any GCR support. I am still waiting for game that requires it.. (It has been very long wait).
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20 September 2018, 20:01 | #4 | |
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Quote:
Alternate Reality The first Amiga game found that has a GCR encoded track. |
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20 September 2018, 23:44 | #5 |
CaptainM68K-SPS France
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21 September 2018, 00:27 | #6 |
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Then don't make us wait, does it have any GCR tracks
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21 September 2018, 13:00 | #7 |
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I am waiting for image. If there is image format that supports it today..
I guess technically it should work with any raw format but different bit density may cause issues if emulator can't know if track is 2us or 4us or even worse, single track has both densities.. |
21 September 2018, 13:12 | #8 |
CaptainM68K-SPS France
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ok, i will post it tonight
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21 September 2018, 17:24 | #9 | |
CaptainM68K-SPS France
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Quote:
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21 September 2018, 17:54 | #10 |
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There's really a GCR track on it
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21 September 2018, 18:09 | #11 |
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21 September 2018, 18:26 | #12 |
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Actually the GCR read (track 50) on CTraw image doesn't work (or better, works but the data read is invalid). If you skip the check the game works properly.
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21 September 2018, 18:51 | #13 |
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I added GCR sync emulation support but it does not seem to work.
If at least 9 one bits have been read and first zero bit is detected: sync found, allow DMA. Unless Amiga GCR means something else but HRM says "appl(e) type GCR". Or perhaps parts of whole sync word is also written to memory? |
21 September 2018, 18:55 | #14 |
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Does that imply the 'dump' was bad, the original disk was bad or that track wasn't mastered correctly?
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21 September 2018, 19:00 | #15 | |
CaptainM68K-SPS France
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Quote:
here it is : ADKCON $09E (write) ADKCONR $010 (Read) BIT - NAME - Function ----------------------------------------- Bit 15 => SET/CLR => activated bits or disactivated Bit 14-13 => PRECOMP = those bits contain PRECOMP value : Bit 14 Bit 13 PRECOMP time BIT 12 => MFMPREC => GCR = 0, MFM = 1 BIT 11 => UARTBRK BIT 10 => WORDSYNC => WORDSYNC = 1 activates the GCR synchronisation of the disk controller on the word present in the register DSKSYNC i guess this BIT 10 is what you need BIT 9 => MSBSYNC => MSBSYNC = 1 activates the MSB synchronisation BIT 8 => FAST => Clock rate of the disk controller FAST = 1:2 microseconds/bit (MFM) FAST = 0:4 microseconds/bit (GCR) |
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21 September 2018, 19:10 | #16 |
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Everyone knows that. It is in HRM! It does not tell anything how it actually works. (Just like WORDSYNC, actual exact behavior was not documented).
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21 September 2018, 19:14 | #17 | |
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Quote:
Sure zero is not inserted by DMA because first byte check is for $CC. |
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21 September 2018, 19:18 | #18 |
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21 September 2018, 19:27 | #19 | |
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Quote:
- maximum number of 1 bits consecutive allowed in coding for 1 byte (FF) - a 0 to invalidate the sequence making an impossible pattern - a 1 to the MSB of the next byte to indicate valid data then 'FF' "0" 'CC' it would tell me the first valid byte (CC) after a sync But they are only suppositions EDIT: the single "0" can be interpreted as maximum number of consecutive allowed zero on GCR could be also "00" actual bits, the meaning would not change Last edited by ross; 21 September 2018 at 19:35. |
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21 September 2018, 19:39 | #20 |
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I can't find FF<1 or 2 zeros>CC combination from the track buffer.
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