20 May 2018, 13:45 | #481 | |||||
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Because of Cephes' high precision, which you never end up using any, none of this is really an issue. I'd be much more concerned about calculators that use doubles. Quote:
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Yeah, that might be a problem right there. |
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21 May 2018, 09:25 | #482 | ||||
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That may be possible, but then many original ST programs (including TOS 1.x) would cease to work. |
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21 May 2018, 11:37 | #483 |
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The Coldfire in some ways was restricted over the original 68K. The 68K has a slightly different code format which they simplified on the Coldfire and this causes issues, when coding for compatibility. Also if 32 BIT BCD and using wider tricks was faster, then why did they omit using it in the x86 series and extend to 64BIT?
They state that the x87 FPU was utilised for byte decimal which converts it to floating point but the 68881/68882 did it all differently. What I mean is... that even the Coldfire changed from 80BITs to 64BITs why does it seem restricted? It seems to me that the original 68K and their FPU's were more advanced in some ways, specially when it came to BCD coding. Yet in later tech they removed so much, in favour of redundant instruction sets, meaning less addressing modes. You talk of an OS with no flaws or limits but doesn't the hardware have to be the same, otherwise you are having to code round the issues. |
21 May 2018, 11:59 | #484 | |
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The complexity one removes somewhere, is just moved elsewhere. And moving it from the cpu to the software is really a bad move (at least today where transistor count does not matter much anymore) because there is a lot more software than there are cpu implementations. |
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21 May 2018, 15:02 | #485 | |||
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Also, some examples would be fun. Quote:
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Okay, that might indeed be the case. But don't tell me you can't do an OS similar to AOS. Couldn't you use a version from a 32bit Atari? |
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21 May 2018, 15:03 | #486 |
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21 May 2018, 20:31 | #487 | ||||
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Perhaps. But that would only solve the problem of the OS itself. |
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21 May 2018, 21:07 | #488 | |
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The problem is that nothing is C89 anymore. Plenty of libraries around, just try to compile them with SASC. Perhaps a custom library in 68k assembler wouldn't be a bad idea. Lower than 640x200x2bpl isn't supported on OCS? Realaly? Yeah, perhaps AOS isn't a good candidate if you want to keep it fast. |
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21 May 2018, 22:06 | #489 | ||
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A custom library in 68k asm is also a good idea. It's not that ! Minimum is OCS. And OCS is 320x256x5 and 640x256x4. If the hardware does not support these, it's under the minimum. M'kay ? |
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21 May 2018, 22:35 | #490 | |
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If you mean Lua code, then all I have is in the archive. If it's C, then you need the Cephes library object file and link it to your own test program because I have nothing that runs directly.
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Right, that's what you mean If this is a stone cold requirement of the default monitor, then it's indeed not going to work. |
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21 May 2018, 22:48 | #491 |
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@ Thorham, meynaf
You are just about to prove, that two people can hold a monolog. |
21 May 2018, 22:54 | #492 | |
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Seems the guys over at FPGAarcade had more or less the same idea: http://www.fpgaarcade.com/punbb/viewtopic.php?id=1310 rebuild the chipset in the FPGA and make use of a fast CPU via JIT. |
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21 May 2018, 23:05 | #493 | |
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The two biggest problems are - the CPU instruction sets and endianness. (but can probably be "solved" with FPGA supported JITs..) - the unsolved ownership of everything "Amiga" :-( So lets call it "Agima" |
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22 May 2018, 08:03 | #494 | ||
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People who don't like emulation won't like it - because it is emulation. And people who like emulation already have a better solution. |
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22 May 2018, 08:12 | #495 | |||
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And of course we could write an OS that is similar But... who would attempt such a daunting task, for so little result ? |
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22 May 2018, 09:14 | #496 | ||
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But granted: it needs to provide a somehow "better" solution. So it should at least feel as native as possible and not like an emulation - e.g. booting directly into AOS, no visible sign of any other OS, a dedicated machine for the Amiga-experience It should be compatible but fast and at least rival WinUAE speedwise. And maybe feel less "JIT-like" (which is fast but with latency) Since we do not have a new fast 68k-ASIC and of course no new Amiga-like chipset, a compilation of the best (affordable) technologies that are around should be taken into consideration, don’t you think? |
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22 May 2018, 10:03 | #497 | |
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The AOS API has now been recreated at least 3 times with 4.x, MOS and AROS. |
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22 May 2018, 10:45 | #498 | ||||||
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That's still better.
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So you need something more clever than just having the onboard cpu execute the code. And it would be safer to target somewhere between vampire and winuae-jit on core i7. That will be difficult. JIT have latencies more or less by design. And no JIT means too slow. Or maybe you have a nice idea to overcome these ? Quote:
I think we should aim for something that adds interest to the platform. Something that would make the platform more enjoyable to code on, so that old coders / demomakers will come back. Quote:
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The OS itself is not enough to make an Amiga. Besides, the APIs are actually the weak point for a coder like me. They're not so practical to code for. And the 68k, while great, has some design issues. Same story with the hardware. So perhaps the best way would be to build a new platform more or less from scratch, respecting the spirit that made the Amiga a great machine, and use emulation for compatibility. What do you think about it ? |
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22 May 2018, 12:34 | #499 | |||||||
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(and there its always the multiple-instances/sandbox/cluster approach that could make use of more cores and level the field a little bit) Quote:
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To speed up the first-round(s) of code-execution and reduce the lag, it is probably a good idea to "outsource" some of the work onto dedicated hardware (FPGA). First step would be a fast 68k-instruktion decoder/translater. Thereby one would need to use all sorts of tricks like instruction bonding or recognition of some very often used tuples of instruction and their shortest representation in the target-ISA. We would need to evaluate where to place the memory controller: using the (mostly faster) host CPU for that or is some extra channel for the FPGA-part better? The second approach would allow to take care of the endianness swapping in the FPGA before handing data over for calculation to the host cpu. It could also take care of some memory operations, that would just be very slow on a risc CPU, directly ... (and we could implement your idea of a dedicated MMU and/or protection unit) Hotspots in the code would than be translated and optimized by the software-JIT .. preferably in parallel by a second core. Very hot hotspots could than again be compiled into VHDL for live updating the FPGA - could be working for things like a ray-tracer or fractal generator. But more clever ideas are welcome! Quote:
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but yes: I like the idea, but this opens of course a myriad of possibilities how to do things OK - lets just concentrate on one element for now: What should the cpu look like? Last edited by Gorf; 22 May 2018 at 13:45. |
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22 May 2018, 13:24 | #500 |
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