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Old 11 March 2017, 07:59   #381
Mathesar
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Thumbs up Nice progress!

The 030 board turned out very nice

About the rev 5 board, the A500 I picked up is also a rev 5 motherboard which has the same ROM issue. You will need to do some hacking to have the 3.1 ROM work. What we would really need for a nice A500HD WHDLoad machine is a 1.3 ROM + scsi.device but the info I could find is not very encouraging: http://eab.abime.net/showthread.php?t=77782. Maybe we could fit a reduced version of kickstart 3.1 in a 256k rom?

Also, the memory priority issue you see is a kickstart 1.2/1.3 issue:
http://eab.abime.net/showpost.php?p=975401&postcount=4
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Old 11 March 2017, 08:17   #382
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A500 woes...

The A500 I picked up needed some work after all.

The floppy was acting up and I suspected a broken drive belt. Should have remembered that 3,5" floppies don't have a drive belt .
It turned out some electrolytic capacitors on the motor drive had started leaking causing the motor to spin too fast. I have replaced the capacitors and now the speed is normal again but the floppies are not always recognized on boot. I think I will also have to realign the heads.

The keyboard was also acting up but I have fixed that by resoldering some bad joints on the keyboard controller.

I am still planning to do a TF-style open-source expansion but I am wondering how useful a TF520+fastmem would be. After all, everybody also wants a harddisk so in the end it would look very much like a TF530.

I therefore want to do a simple HD expansion + some fast mem. A bit like the kipper2k board but then open source.

I have some ideas that would do away with the OVR and _INT2 patches and would also allow the use of SD-cards instead of compactflash

The idea to get rid of OVR is this:
On A500, the gayle IDE area is allocated by the chip registers. If we don't pass AS/UDS/LDS upon acessing this area to the mainboard what will gary do? Or if that doesn't work spoof gary into thinking we are writing to some unused address space by modifying the address lines.

For _INT2:
We could just monitor all writes to paula to keep a shadowed version of _INT2 and use that to inject _INT2 into the IPL signals.

What do you think? Possible ?
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Old 11 March 2017, 08:26   #383
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Quote:
Originally Posted by jediknight View Post
be good if they had a decent amount of memory on it but for the price of making one could get an old 030 with loads of memory on it really.


I think it depends on what the goal of the project is. As far as I can tell; plasmab is mostly doing it for creating a cool accelerator everyone could make themselves and expand on the designs. The biggest part is mostly learning and then designing an accelerator for the CD32. But hey, if you can do a better job, I would love to see that project materialise as well Plasmab is delivering a great stepping stone for you to start.
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Old 11 March 2017, 08:51   #384
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Originally Posted by Mathesar View Post
I am still planning to do a TF-style open-source expansion but I am wondering how useful a TF520+fastmem would be. After all, everybody also wants a harddisk so in the end it would look very much like a TF530.

I therefore want to do a simple HD expansion + some fast mem. A bit like the kipper2k board but then open source.

I have some ideas that would do away with the OVR and _INT2 patches and would also allow the use of SD-cards instead of compactflash

The idea to get rid of OVR is this:
On A500, the gayle IDE area is allocated by the chip registers. If we don't pass AS/UDS/LDS upon acessing this area to the mainboard what will gary do? Or if that doesn't work spoof gary into thinking we are writing to some unused address space by modifying the address lines.

For _INT2:
We could just monitor all writes to paula to keep a shadowed version of _INT2 and use that to inject _INT2 into the IPL signals.

What do you think? Possible ?
So on the TF530 OVR is gone really. So yes.. we are able to hide gary that way... I dont let AS get to the A500 if the cycle is internal. I just have it for belt and braces. I planned to do the IPL trick on the TF530 rev 3 if i ever make one. Just needed to go in small steps.

TBH sounds like you have gone down the same thinking route I did... You're going to end up with the TF530 again... which is not bad.. Maybe just RIP up the static ram and try routing dram? If you keep everything else the same you should even be able to merge changes i make to the rest of the board?
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Old 11 March 2017, 11:54   #385
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Hi plasmab,

First I must thank you for the good job you're doing on the TF accelerators

In the Commodore Amiga Facebook group we're trying to do a group purchase of the TF530 PCB & parts excluding the CPU/FPU. This initiative was started by Christopher Gaul over at the Google+ Commodore Group.
I could post the links here but I don't know if this is allowed by the EAB rules! Could an admin clear this out please?

One of the members of the Commodore Amiga fb group was asking if it was possible to put more than 2MB of SRAM on the actual TF530 board?
Are there any other tips regarding the TF530 you can give us to make this initiative feasible?

All the best,
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Old 11 March 2017, 13:12   #386
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Originally Posted by MoRetro View Post
Hi plasmab,

First I must thank you for the good job you're doing on the TF accelerators

In the Commodore Amiga Facebook group we're trying to do a group purchase of the TF530 PCB & parts excluding the CPU/FPU. This initiative was started by Christopher Gaul over at the Google+ Commodore Group.
I could post the links here but I don't know if this is allowed by the EAB rules! Could an admin clear this out please?

One of the members of the Commodore Amiga fb group was asking if it was possible to put more than 2MB of SRAM on the actual TF530 board?
Are there any other tips regarding the TF530 you can give us to make this initiative feasible?

All the best,
It is possible if you can find the SRAM chips.. AS7C38096A 5V 10ns will work. I have no idea where to find these guys though and it will need a minor firmware patch to the zorro config but that is trivial.

If you guys find any of the AS7C38096A chips then let me know.

You should also help me with the wiki on the github page..

https://github.com/terriblefire/tf530/wiki

It would be best to keep all the build information there.
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Old 11 March 2017, 15:41   #387
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Thanks plasmab, for the quick reply

Noob question: Could you forsee somekind of stepdown volt regulator to facilitate the use of the more readily available 3V SRAMs?

All the best,
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Old 11 March 2017, 17:17   #388
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Originally Posted by MoRetro View Post
Thanks plasmab, for the quick reply

Noob question: Could you forsee somekind of stepdown volt regulator to facilitate the use of the more readily available 3V SRAMs?

All the best,
We could use the 3.3V rail that is already there but we would also need to stepdown the CPU data bus *AND* address bus... thats a lot of pins to buffer. (32+18)... and it wouldnt fit on the board.
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Old 11 March 2017, 17:48   #389
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Thanks for your reply Plasmab

Robert Miranda from the Commodore Amiga fb group has following question:
Quote:
"I haven't looked over all of the details, but a question comes to mind: Does any of the memory options allow the 32-bit SRAM to get placed above the 16MB address point (i.e not in the AutoConfig space)? and second, if only in the Zorro II AutoConfig space, does it support DMA? (i.e A590, GVP A500-HD8, possibly other non polled-I/O)"
Can you comment this please?

All the best,
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Old 11 March 2017, 18:08   #390
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Originally Posted by MoRetro View Post
Thanks for your reply Plasmab

Robert Miranda from the Commodore Amiga fb group has following question:


Can you comment this please?

All the best,
Its pure zorro-II autoconfig ram. No DMA possible.
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Old 11 March 2017, 18:24   #391
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I've started the wiki. Please add issues ommisiont to the issue tracker.
https://github.com/terriblefire/tf53...m-Architecture
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Old 12 March 2017, 04:06   #392
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Originally Posted by Mathesar View Post
The 030 board turned out very nice

About the rev 5 board, the A500 I picked up is also a rev 5 motherboard which has the same ROM issue. You will need to do some hacking to have the 3.1 ROM work.
The Rev 5 is a bit of a pain if you want a 512k/1024k ROM. But you can use an extra 40-pin socket without harming your motherboard. It's ugly but it works.
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Old 12 March 2017, 09:01   #393
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I have googled around and it seems that even with the byte/vpp hack you can get problems on a rev5. What is also needed is some pullups on the address lines: http://eab.abime.net/showthread.php?t=82824

The pullups could be easily added on the TF530 itself. (and maybe they are not needed with a 030?)
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Old 12 March 2017, 09:17   #394
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Found my project

OK, I found my first project to help out on the open-source accelerator initiative.

I plan on using a Cypress PSOC5 to implement a SD-card based harddisk controller. For those who don't know the Cypress PSOC; the PSOC is a "programmable system on chip". It contains a 67..80MHz ARM processor (so far nothing special) but... it also contains a PLD and some configurable analog blocks. The PLD part is what makes the PSOC so interesting because we can use that to implement glue logic, gayle emulation, zorro-II, etc, etc. It can thus fulfill the role of the Xilinx chips on the TF520/TF530.

See attached the block diagram of the CPLD part:

Each UDB contains 2 12c4's (8 product term's, 4 flipflops) and a datapath (ALU, some registers and two datapath FIFO's to communnicate with the main CPU). So, it's not a huge CPLD but actually quite capable for what we need.

But the really good part is: The Cypress chips run on 1.7 to 5.5V (and even have multiple IO banks which can run at different voltages), they cost less than 7 euros at Mouser and you can buy an evalution kit for 10 euro's which can be turned into a programmer. The software is completely free and "understands" verilog

The particalar type I'm after: http://www.cypress.com/part/cy8c5467axi-lp108

If I can get a gayle/ide emulation to run in this thing the circuit will be extremely simple, basically only the PSOC chip and a flash card connector.

So, this is my project; a building block for future accelerators and a proof-of-concept to use a PSOC as an alternative CPLD.
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Old 12 March 2017, 11:02   #395
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Nice!! You could try replacing the RAM cpld only in the first instance. What do we get from this though? You are stuck at Gayle speed unless you buffer the busses


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Old 12 March 2017, 13:52   #396
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Nice!! You could try replacing the RAM cpld only in the first instance. What do we get from this though? You are stuck at Gayle speed unless you buffer the busses
The gain would not be so much speed but simplicity.
I hope that I can eventually create a TF522 with only 3 chips: 16mbit RAM, PSOC and 68020.

But even using only the digital part of the PSOC would already be interesting as it is basically a 5V capable CPLD that can be programmed by a cheap programmer. Even better; by using the USB bootloader any user could upgrade the logic without the need for a programmer at all. What is also nice; the PSOC has a built in PLL that could lock onto the 7mhz signal to make the accelerator synchronous.

Last edited by Mathesar; 12 March 2017 at 14:10.
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Old 12 March 2017, 17:07   #397
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The gain would not be so much speed but simplicity.
I hope that I can eventually create a TF522 with only 3 chips: 16mbit RAM, PSOC and 68020.

But even using only the digital part of the PSOC would already be interesting as it is basically a 5V capable CPLD that can be programmed by a cheap programmer. Even better; by using the USB bootloader any user could upgrade the logic without the need for a programmer at all. What is also nice; the PSOC has a built in PLL that could lock onto the 7mhz signal to make the accelerator synchronous.
FWIW decided not to go that route because it needs higher pin density chips which are harder to solder. You'd need A23-A12 + A6-A0 on the CPLD + D31-D24 and all the bus logic pins... So you're talking a 144 pin TFQP. I could have made all this fit on a 144 CPLD (and it would have been simple) but I doubt you'd be able to route that on 10cm x 10cm and the soldering would be harder..

Just saying i rejected that approach already for the above reasons. Unless you want epic routing pain stick to 2 chips.
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Old 12 March 2017, 18:20   #398
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@plasmab
I got some info for you from Robert Miranda.

Quote:
Robert Miranda
An observation based on the alpha/beta board in the pic - With an EC 68030 (which some may choose for cost/speed reasons), that implies no MMU for one of the more useful speed improvements, which is Kickstart remap to 32-bit RAM.

An address decode trick can be done with an aligned chunk of RAM (to the OS ROM), as in the top or bottom 256K/512K/1M of the 32-bit onboard RAM, which is unlikely to be used / is free at boot time. You actually may incur no potential MMU memory wait state this way, or conflict with any MMU tools, too, in the process. GVP G-Force boards (68030, and the 68040) with or without EC parts can do that, and I know other third party boards do it, too.
Quote:
Robert Miranda
A note about the design going to 50Mhz - you won't fine anything but PGA FPUs at that speed (I think 40Mhz is the cutoff for PLCC 68882's). Consider a rework for PGA on the math chip in a future board revision, or plan for a separate (slower) clock on the FPU.
All the best,

Last edited by MoRetro; 12 March 2017 at 18:34.
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Old 12 March 2017, 18:25   #399
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Quote:
Originally Posted by MoRetro
Thanks for your reply Plasmab

Robert Miranda from the Commodore Amiga fb group has following question:


Can you comment this please?

All the best,
Its pure zorro-II autoconfig ram. No DMA possible.
A reaction from Robert Miranda:
Quote:
Robert Miranda Noted and thanks (to both of you) for the answer.

So the technical answer is clear to others reading: Anyone with a C= A590, or the GVP Series II A500 will have problems with the non-DMA capable 32-bit RAM in Z2 AutoConfig space. The HD8 will also need to be set for the RAM 2MB or 4MB setting (and use 4x1MB modules). The 8MB setting will fail to AutoConfig (not enough room). I can't speak for any other A500 external peripheral on DMA, but if any have 8MB in them, they would also have to set it lower.

Both C=/GVP: Historically, the likely suggested DMA mask hack will either kill performance, or be ineffective. Mountlist/RDB mask only affects file system level communications, and not low-level direct SCSI communications - like the partitioning config tool, which may not see anything depending on the RAM it is given to communicate data transfers through - which can vary.

I don't want to be a killer of the project's enthusiasm, so I'll toss in a few ideas for future consideration, maybe for use in other projects:

That 2MB SRAM bank, not supporting DMA, belongs above the 16MB boundary on any system host that is 24-bit, or at least allow it to be optionally located there. By Commodore bus design, Zorro II RAM space (200000-9FFFFF) should be DMA'able. Putting RAM high would match a number of other expansion accelerator products that don't support DMA to their memory (CSA MegaMR, VXL-30, and others). AddMem is a solution in that case (the quick fix). Running a number of tools after that command (CPU/SETCPU FastROM, movevbr, etc) would bring/move a number of OS pointers, tables, code, & vectors into the faster (preferred) 32-bit zone.

As the product seemingly has hooks into AutoConfig? then consider maybe this: Map a small 16K I/O board (not of type RAM) in AutoConfig that lets you match it to a Binddrivers (Expansion Drawer) driver at startup-sequence boot. Your driver, when called and matched to the board, could then call the equivalent of an AddMem command, and insert the memory range via software. It could be made to perform a number of the remappings other tools do separately, too, just match the tooltype option to activate it.

At some point in the future, a ROM could be placed within that I/O card definition space, and it could do some of the same, and/or possibly include the IDE interface code (I will assume, knowing nothing right now but owning an IDE68K, that it likely relies on an A600's v2.05/3.x (37.300+ with A600 IDE support) OS ROM if it's interface is bootable.

For any other future/related projects, that small I/O board hook leaves many options one can handle at a software level, at least as testing is concerned. Note that all of the GVP A2000 030/040 products map all of their >16MB addressed 32-bit memory via that device driver ROM. Others may have chosen to do that method, too.

I hope that helps. I am still interested in the board.
All the best,
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Old 12 March 2017, 20:08   #400
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So the technical answer is clear to others reading: Anyone with a C= A590, or the GVP Series II A500 will have problems with the non-DMA capable 32-bit RAM in Z2 AutoConfig space. The HD8 will also need to be set for the RAM 2MB or 4MB setting (and use 4x1MB modules). The 8MB setting will fail to AutoConfig (not enough room). I can't speak for any other A500 external peripheral on DMA, but if any have 8MB in them, they would also have to set it lower.
I think that these are non-issues for the typical use-case for the TF530. I mean, when I had my A500 back in the days I had 1 meg of RAM (512k + 512k) and an extra external floppy. That was also what my friends had. I have never seen an A590 or GVP harddisk back in the days. It was simply too expensive for the typical 15 year old. It wasn't until the A1200 came along that CPU upgrades and such became populair.

So now, in 2017, you can pick up a second hand A500, clean it, fix it up, retrobrite it and put in a self-built 68030 card with a harddisk! How cool is that? And who cares it won't play nice with an A590?
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