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Old 26 December 2009, 21:56   #66
yaqube
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Join Date: Mar 2008
Location: Poland
Posts: 158
I have made some tests with an OCS Denise and a logic analyzer. I was wrong thinking that the OCS display window generation is considerably different than the ECS.

I can confirm all Toni's observations. During normal display hdiwstrt < 2 doesn't enable the display window. Also hdiwstop > 455 ($1C7) doesn't disable it. Exactly the same way acts an ECS Denise.

As Tony has noticed something interesting happens during display lines 0-8. The display window is enabled there. And I think I have found an explanation.

During first 9 display lines (0 - 8) register $038 (STREQU) is written (the write takes place during first refresh slot). That's a time when serration and equalization pulses are generated for CSYNC. Then during lines 9 - 25 (PAL) register $03A (STRVBL) is written.

It seems that writing $038 register doesn't reset (exactly doesn't set to 2) the hpos counter inside Denise. This counter is probably 9-bit wide and rolls over a few times during this period. That's why start condition of hdiwstart < 2 is satisfied. Also any hdiwstop is satisfied but at the end of the 9th line the hpos counter counts only to (455 + 9*454) % 512 = 445 so if hdiwstop > 445 the display is enabled.

If you wonder what the above numbers mean here is a brief explanation:
455 - last hpos value during the last display line
9 - number of lines when $038 strobe register is written
454 - line length (227 CCKs)


In ECS Denise this design omission has been fixed and that's why hdiwstrt < 2 doesn't enable the display window.

Last edited by yaqube; 27 December 2009 at 10:31.
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