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Old 07 November 2019, 12:27   #27
ross
Per aspera ad astra

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Join Date: Mar 2017
Location: Crossing the Rubicon
Age: 49
Posts: 2,348
Thank you all for your answers and suggestions.
I just have to digest the whole thing (I still have some doubts ).

Quote:
Originally Posted by dissident View Post
My post from 24 January 2019, 09:30 in my thread may help you and make things clearer.
Yep, very helpful And thanks for various links.

Quote:
The question is what you want to set at boot time. The caches are turned off and the cashmodes are like I explained in this thread.
Usually I disable all caches for old games and/or compatibility.
But for a proper patched game, ICACHE would be better to be on (to speed-up unpacking and similar).
Seems that some 040/060 Amiga accelerators use MMU right at cold start, so a proper handling is due.

Quote:
Originally Posted by phx View Post
Im using the following code in my games (started with trackloader from the boot block), while the OS is still alive:
Thanks phx, the part 2) is what I'm talking about.
There are a couple of instructions that I am not convinced of, but I have to do some tests first and then ask you questions

Quote:
Originally Posted by Thomas Richter View Post
That is (almost) correct. To be more precise: The 68040 and the 68060 have a "push buffer" into which they can perform a write while the bus is busy, and execute another instruction while the write is being piled up.

However, to activate this push buffer, the caching mode of the chip memory has to be set accordingly, namely to "non-serialized" on the 040 and "imprecise" on the 68060.

If the caching mode is "cache inhibited", then writes will also stall the 68040 and 68060 as it then guarantees purely sequential operation.
Ok, and this can be done also with only xTT registers with MMU disabled.
But how the global DCACHE active bit affect the memory access?
i.e if I global disable data cache, the access could be still non-serialized?

Cheers.
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