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Stedy · 05 March 2014, 00:59

Hi,

@alexh

Thank you for the source code conversions. You've given me a few ideas to play with and I can see how many resources I need in some candidate CPLDs.

Would you have a testbench for a 68020 processor interface?

@thread

Don't expect a quick design turnaround. All going well, might have something around May, assuming a couple of other projects go Ok.

Can I also ask for some feedback on a few ideas?

I assume you would prefer to use and source your own SIMMs, upto 8Mb rather than have SRAM onboard?
4 MB SRAM costs £10, 8 MB costs £20

For IDE I'm planning to fit a compact flash connector, any objections?

For a floppy interface, a 34 pin header is easier and cheaper than 23 way d-types for external drives.

A CPU/FPGA accelerator would be a later design, depending on how this design progresses and the CPU cores themselves. It would of course cost more.

Ian

05 March 2014, 00:59	#121
Stedy Registered User Join Date: Jan 2008 Location: United Kingdom Age: 46 Posts: 733	Hi, @alexh Thank you for the source code conversions. You've given me a few ideas to play with and I can see how many resources I need in some candidate CPLDs. Would you have a testbench for a 68020 processor interface? @thread Don't expect a quick design turnaround. All going well, might have something around May, assuming a couple of other projects go Ok. Can I also ask for some feedback on a few ideas? I assume you would prefer to use and source your own SIMMs, upto 8Mb rather than have SRAM onboard? 4 MB SRAM costs £10, 8 MB costs £20 For IDE I'm planning to fit a compact flash connector, any objections? For a floppy interface, a 34 pin header is easier and cheaper than 23 way d-types for external drives. A CPU/FPGA accelerator would be a later design, depending on how this design progresses and the CPU cores themselves. It would of course cost more. Ian