Quote:
Originally Posted by ross
ipl=6 doesn't allow any maskable IRQ (same as 7)
ipl=0 allows >0, so every IRQ
ipl=1 allows >1, and so on
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In my memory it did put level+1 in ipl field when an interrupt occurs. I guess it's been too long i haven't fiddled with these...
But then ipl=7 would mask level 7 but they just prevented it ?
Quote:
Originally Posted by ross
Well, I can understand for the listed instructions, that are all with modification of the destination, but not for a read only operation!
(if same die part is used for this operation is sure a bad implementation, but ehi, is a 1979 project with limited transistor usable  )
I must always remember not to use it 
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The CLR bug is a strong hint in that direction anyway. Damned electronicians always take shortcuts where they shouldn't
Another reason for me to prefer coding on 68030
