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Old 22 June 2017, 00:12   #155
matthey
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Join Date: Jan 2010
Location: Kansas
Posts: 1,284
Quote:
Originally Posted by grond View Post
The VSX supports both scalar and vector instructions for both floating-point and integer, all happily mixed into a single register file.
IBM did introduce integer SIMD data into the FPU register file but integer is faster than floating point processing so nothing is slowed.

Quote:
Originally Posted by Workload acceleration with the IBM POWER vector-scalar architecture (Figure 1)
The 64-entry vector-scalar register file. The new VS register file with 64 vector-scalar registers (VSR) is created by extending the 32 floating-point registers (FPR) to 128 bit and combining them with 32 AltiVec registers (VR).
Introducing slow floating point into the fast integer units can slow the integer unit processing of the most important and time sensitive part of the CPU. More ports may be required for the register file potentially slowing it. Enlarging the integer unit register file for more SIMD registers is also potentially slower. These are poor choices for energy efficiency if ever moving to an ASIC as well.

You talk about education but what good is it when you deny what you have learned and the obvious truth? At that point, the only degree you deserve is a degree in propaganda, deception and brainwashing which is good for nothing productive. I hope there are enough critical thinkers here to sort out what degree you deserve.
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