[chb]

Originally Posted by Toni Wilen

Except what UHRES bitplane and sprite pointers do? I assumed content would appear in data bus but data bus is idle (but there is only one bitplane cycle so where the other half of address would go?)

Why would Agnus internally do modulo addition if nothing sees the address?

AFAIU, data bus content is not needed, only the DRAM address bus value if it works like Gorf assumed. RGA value triggers the transfer mode of the VRAM, the address tells the VRAM with ROW to transfer to SAM, (for bpl, for sprite it seems improbable that they read two complete ROWs every scanline, no idea how it would work). I suppose it doesn't matter what is on the data bus during that operation.

Did you also check address bus value or only the data bus?

Originally Posted by Toni Wilen

I think it would work but I am not sure about CSCBEN. BEAMCON0 has so many never used bit combinations and documentation is not very clear..

Yep, it reads like being written by someone who likes good riddles.

Originally Posted by Toni Wilen

Normal primary. HHPOS seems to be only used for UHRES. Chipset display was perfectly normal even when HTOTAL in DUAL mode was zero or one.

Ah, I was thinking that AGA/ECS modes with non-standard timing (Productivity or Euro36/72, maybe also dblPAL/NTSC) also run from the variable beam counter. But I think I misread the BEAMCON0 documentation:

VARBEAMEN
Enables the variable beam counter comparators to operate
(allowing different beam counter total values) on the main horiz
counter. It also disables hard display stops on both horizontal
and vertical.

It probably means it uses HSSTRT etc. on the primary beam counter, not the secondary counter for the main display. But then, how does it work with e.g. Euo72 (24 kHz) mode, if the beam counter is quite out of sync with the actual display? Very confusing.