Quote:
Originally Posted by vriviere
Thanks, everything is clear now.
Just a final remark: Since this "interrupt vector fetch" feature is provided by the interrupt device (= the ROM), it should be associated to the chipset or some other hardware, but not the CPU.
So if I use A500 settings in UAE and I switch to a 68020 CPU, to be 100% logicial the "interrupt vector fetch" feature should remain enabled, isn't it ?
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It is CPU doing the fetch as documented in pages 5-9 and 5-10 (cheap design, chipset does not need any extra support hardware..). No idea about other CPUs but AFAIK it does not happen in 68020+.
I have not done any 68020+/AGA logic analyzer tests, only A500 which clearly shows ROM enable line going active during interrupt initialization.