|
A more problematic aspect than the blitter intercepting the CPU is the CPU intercepting the blitter.
The blitter will fetch from its source channels, then the data is in transit within the blitter for a couple of cycles, then written out to the D channel. Worst case this is 7 bus cycles (ABCD active, A & D point to the same mem location, latency A -> pipeline -> D) ignoring other DMA. If the CPU modifies the memory location during those 7 bus cycles, the CPU result of the CPU operation will be overwritten by the blitter.
|