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Old 22 November 2020, 17:23   #5
SpeedGeek
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Join Date: Dec 2010
Location: Wisconsin USA
Age: 57
Posts: 567
Sorry, no benchmarks. Some benchmark programs just report the E clock frequency but never bothered with performance results for the E clock bus. Chip RAM is not relevant since it's timing is on the 7 MHz bus.

Some Approx. 7 MHz wait state calculations are as follows:

Old U506 PAL
---------------
Best case 8 clocks
Worst case 17 clocks

New U506 GAL
----------------
Best case 5 clocks
Worst case 14 clocks

Notes: The number of CPU wait states varies with the CPU clock speed and the efficiency of the 68000 state machine logic. Also, the average case performance is much better for the new U506 GAL since it runs the case 3 cycle and the old U506 PAL skips it. Yes, it could be tweaked in a CPLD based design too.

Last edited by SpeedGeek; 24 November 2020 at 15:00.
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