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Old 22 November 2020, 13:27   #4
PR77
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Join Date: Oct 2017
Location: Germany
Posts: 185
This is a very interesting idea ... Do you have some benchmarks for comparison? With only Chip RAM present?

For newer accelerators which generate an E Clock (mine inclusive) based on the original timing (E Clock active -> /DTACK assertion) this would not be too hard to also tweak in the CPLD.
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