[Stedy]

Originally Posted by plasmab

I've been digging through the Xilinx reports generated by the fitter. I then wrote some parsers in python to compare what I expected the pinouts to be vs what Xilinx set them as. There is a mismatch!!

TF530 Rev2

stephen@debiandev:~/git/tf530/build$ ./validate.py rev2 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 60 PIN: IPL<2> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: IPL<1> UCF: A<13> Error
Checking pin 57 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 UCF: A<13> PIN: IPL<1> Error
Parsing Pinfreeze File: work/ram_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 46 PIN: EXTINT UCF: Error - PIN NOT IN UCF FILE!

TF530 Rev3

stephen@debiandev:~/git/tf530/build$ ./validate.py rev3 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev3.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 34 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: DSACK<0> UCF: A<13> Error
Checking pin 43 UCF: A<13> PIN: DSACK<0> Error
Parsing Pinfreeze File: work/ram_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev3.ucf .... Done

I checked the UCF files/schematic and fitter reports and found something else.

A13 is an unused input and was optimised out by the fitter.
IPL1/2 connect from the 68000 socket to the 68030, not to the CPLD. I removed them.

Comparing the Rev 2 UCF aginast Rev3 and the schematic, I saw the following errors

Signal   Rev 2 pin     Rev 3 pin  Schematic
AVEC    35                63           35
DSACK0 63             MIA         63
FC0       34               40           34
FC1       33               35           33

After making those edits and adding a timing constraint on the clock from the V2 file, I rebuilt the design and checked the fitter reports against the schematic. Attached is a JEDEC file to program the board, new UCF file, ISE project file and the Verilog source. Can someone try the attached image and report their findings?

Ian