Second time today I post this link:
http://amigadev.elowar.com/read/ADCD.../node0161.html
Quick explanation: 68030 data cache always caches long aligned writes, even if destination address is supposed to be uncacheable. Following read(s) from same address come from cache, not from memory that may have been modified by some DMA device.
AFAIK this can be only fixed by using MMU to mark required memory regions as uncacheable. (if CPU is non-EC)