Thread: Copper timing
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Old 20 July 2008, 17:01   #16
yaqube
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Join Date: Mar 2008
Location: Poland
Posts: 158
"/BLIT" is another name for "/DBR". In all functional descriptions in Technical Reference and Service Manuals for A500/A2000 the name "/DBR" is used but in schematics it's named "/BLIT". It prevents CPU from getting bus access in current cycle.

"/REGEN" is an output from CPU address decoder. It's only active when CPU wants to access custom registers.


Quote:
COPJMP cycle usage seems to be:

1:fetch copper instruction (normal move cycle 1)
2:write to copjmpx (normal move cycle 2)
3:fetch next instruction(write to copins. I really need to see data in data bus..)
4:use another cycle for nothing (copy internal pointer?)
5:continue normally
According to my tests:

As for 3: it apears that this cycle doesn't have to be a write to copins. It can also be a bitplane dma fetch.

As for 4: it apears that this cycle must be a free bus cycle. If it's taken by bitplane dma another cycle is required.
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