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Old 29 January 2014, 13:42   #4
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Join Date: Jan 2004
Location: Oxford
Posts: 12,222
For IDE we should be able to re-use the Gayle IDE re-implementation from the CFIDE68k project. However I believe that is written in ABEL which isn't a particularly flexible HDL.

Once converted to VHDL/Verilog you won't need to use the same CPLD. You could use a larger one with enough pins and slices to implement either SRAM or DRAM memory expansion.
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