[Megol]

Originally Posted by meynaf

Have i been so rude ? Why destroying posts like this ?

Because it doesn't make any difference.

Unreadable to say the least !

BIC = bit clear
NE = execute on Not Equal = Z condition code clear
No S = doesn't set flags

R0, R1, R2 ASR R3 ; R0 = R1 op (R2 ASR R3)

For what ?

For example if R2 is negative one can clear a bitfield from the MSb towards the LSb with the size specified in R3. So bitfield operations.

BEQ .skip
ASR.L D3, D2 ; D2 = D2 ASR D3
NOT.L D2 ; ...
AND.L D1, D2 ; D2 = D2 AND D1
.skip

Note that I selected this instruction to illustrate a point. One 32 bit RISC type instruction doing the work of 4 68k instructions 64 bit in total.

While being easier to decode, faster to execute and not overwriting potentially useful data.

I tried this for my ISA. Ended up eating as much encoding space as the whole branch instruction, and unable to replace it as other instructions than CMP also set useful flags.

Those aren't meant for size optimization but to enable one instruction to both do an operation and branch on condition.

The hardware costs for this is slim, each instruction would set the condition codes anyway, comparing condition codes against a specific condition is trivial and the ALU would only need to give the result to the branch unit.

The complication in the decoder is how to extract the condition field and detect (and extract) the branch address. Trivial.

Sadly the semantics of DBcc makes it hard to do in one standard instruction but op+branch still makes it easier to translate.

That would be simpler with an EXG instruction.

Yes and shows that ARM isn't the perfect instruction set.

Not being able to do something like:

ADD R0, R1, #1 LSL R1

Is also sad.

That most instructions waste 4 bits is insane, that the PC is a general register a problem, that it only have 15 normal registers another.

Indeed, and two instructions actually 25% larger in size than the 3 classical ones used for this...

But faster to decode and execute while requiring less transistors. Which is why RISC was created in the first place - to be more efficient to execute.