Quote:
Originally Posted by grond
"The VSU features a large number of new instructions and
architectural refinements for applications like business
analytics, big data, string processing, and security. The VSX pipelines now supports 2-way 64-bit vector and 128-bit scalar integer data types and new direct GPR-to/from-VSR move operations that provide a fixed-latency and high bandwidth data exchange between the vector and general purpose registers. The added VMX crypto instruction set is targeted towards AES, SHA2 and CRC computations and several instructions have been promoted into VSX to gain access to all 64 architected vector registers."
The VSX supports both scalar and vector instructions for both floating-point and integer, all happily mixed into a single register file.
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I'm not too familiar with the POWER8 arch, but your quote clearly states "GPR-to/from-VSR move operations", which would imply separate GPR & VSR regfiles. So, it looks like it does have separate 'integer-only' regular general purpose registers and separate 128x64 VSR registers. Which in my opinion, makes perfect sense, as using just a single 128x64 regfile for all ops would push power usage much higher.
Now, that doesn't mean that ops on VSR can't be integer, because, why wouldn't they be - even GPUs can do integer math.
The issue with separate regfiles is not (just) of frequency, but mostly power. Look at the latest Intel's AVX512 - power usage is quite a lot higher then previous versions. It just doesn't make sense to use such large regfiles for all operations.