Thread: 8 meg agnus mod
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Old 12 March 2019, 19:02   #16
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 45
Posts: 23,679
Perhaps it would work after all.. Megachip like extra board with Agnus socket + 2M or 6M of RAM (or perhaps it is easier to have all chipram on board) + FPGA + 1 or 2 address lines that needs connecting to CPU pins.

FPGA could snoop RGA bus addresses and store extra 2 address bits for each xPTH (High word DMA pointer) register when written. (Even internal Agnus register accesses are visible in RGA bus which enables storing copper writes)

When Agnus does DMA, FPGA would match RGA bus value with stored DMA pointer value and set chip ram extra 2 address bits to select correct 2M chip ram "bank".

(DMA crossing banks needs extra care but it should be simple enough to handle by comparing if previous same DMA channel's memory address value was very large and new very small or vice versa)

I think this should work, assuming there is time to snoop RGA bus and select correct extra chip ram "bank" before Agnus does the DMA transfer.
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