English Amiga Board - View Single Post - Pacman - the Amiga conversion from the arcade game

mcgeezer · 10 September 2019, 18:11

So I had a bit of a further think about this, apologies but I haven't been able to test any of it yet.

@mods - you might want to move this into a technical section.

I'd setup my z80 -> 68k registers like below, the I register does not seem to be directly updated.

Code:

REGISTERS:
	A	equr	D0
	B	equr	D1
	C	equr	D2
	D	equr	D3
	E	equr	D4
	H	equr	D5
	L	equr	D6
	HL	equr	A0
	BC	equr	A1
	DE	equr	A2
	IX	equr	A3
	IY	equr	A4
	SP	equr	SP
	SCRATCH	equr	D7

The high word in D7 would be set to Amiga Chip ram 64Kb page where the PACMAN rom is actually loaded as per the... MAME driver doc: https://github.com/mamedev/mame/blob...ers/pacman.cpp
A5 would probably point to the top of the Amiga copper list or Chip base
A6 would point to something sensible.

I'd approach this by using a translator that reads the rom code section and creates equivalent 68000 code, all of the instructions that relate to branches/loops would need to be calculated and the status register honored.

If any of Z80 instructions update a register I would create code from the macros below. (i.e. if address reg HL updates then the H and L data regs must be updated too. This will probably be fast enough.

Code:

; Update 8 bit regs...
UPDATE_DATA_HL MACRO
	move.l	HL,L			; HL into H
	move.w	L,H			; L done
	lsr.w	#8,H			; H done
	ENDM
	
UPDATE_DATA_BC MACRO
	move.l	BC,C			; BC into B
	move.w	C,B			; C done
	lsr.w	#8,B			; B done
	ENDM
		
UPDATE_DATA_DE MACRO
	move.l	DE,E			; DE into D
	move.w	E,D			; E done
	lsr.w	#8,D			; D done
	ENDM
	
; SCRATCH (d7) register holds memory base 64k segment.  for example.... $30000
UPDATE_ADDR_HL MACRO
	move.w	H,SCRATCH			; H into Scratch reg
	lsl.w	#8,SCRATCH			; shift up into high byte
	or.b	L,SCRATCH			; fetch L into low byte
	move.l	SCRATCH,HL			; Update HL
	ENDM
	
UPDATE_ADDR_BC MACRO
	move.w	B,SCRATCH			; B into Scratch reg
	lsl.w	#8,SCRATCH			; shift up into high byte
	or.b	C,SCRATCH			; fetch C into low byte
	move.l	SCRATCH,BC			; Update BC
	ENDM
	
UPDATE_ADDR_DE MACRO
	move.w	D,SCRATCH			; D into Scratch reg
	lsl.w	#8,SCRATCH			; shift up into high byte
	or.b	E,SCRATCH			; fetch E into low byte
	move.l	SCRATCH,DE			; Update DE
	ENDM

I just want to caveat the above with that it would be a fallback when no optimised translate instructions could be used. For example adding 1 to H would go..

Code:

move.w #1,SCRATCH
add.w SCRATCH,HL
add.b SCRATCH,H

As the translated code runs each frame I'd opt for a Copper or VBL interrupt to read the memory mapped IO ports described in the MAME driver, the ISR would effectively do all of the Amiga side screen updates.

The status register could be tricky (would need to store that somewhere possibly in D7?).

One massive improvement a 68020 would have over this is that data regs can be used as address registers, so effectively... it would fly.

Thoughts...? Am i crazy?

10 September 2019, 18:11	#27
mcgeezer Registered User Join Date: Oct 2017 Location: Sunderland, England Posts: 2,702	So I had a bit of a further think about this, apologies but I haven't been able to test any of it yet. @mods - you might want to move this into a technical section. I'd setup my z80 -> 68k registers like below, the I register does not seem to be directly updated. Code: REGISTERS: A equr D0 B equr D1 C equr D2 D equr D3 E equr D4 H equr D5 L equr D6 HL equr A0 BC equr A1 DE equr A2 IX equr A3 IY equr A4 SP equr SP SCRATCH equr D7 The high word in D7 would be set to Amiga Chip ram 64Kb page where the PACMAN rom is actually loaded as per the... MAME driver doc: https://github.com/mamedev/mame/blob...ers/pacman.cpp A5 would probably point to the top of the Amiga copper list or Chip base A6 would point to something sensible. I'd approach this by using a translator that reads the rom code section and creates equivalent 68000 code, all of the instructions that relate to branches/loops would need to be calculated and the status register honored. If any of Z80 instructions update a register I would create code from the macros below. (i.e. if address reg HL updates then the H and L data regs must be updated too. This will probably be fast enough. Code: ; Update 8 bit regs... UPDATE_DATA_HL MACRO move.l HL,L ; HL into H move.w L,H ; L done lsr.w #8,H ; H done ENDM UPDATE_DATA_BC MACRO move.l BC,C ; BC into B move.w C,B ; C done lsr.w #8,B ; B done ENDM UPDATE_DATA_DE MACRO move.l DE,E ; DE into D move.w E,D ; E done lsr.w #8,D ; D done ENDM ; SCRATCH (d7) register holds memory base 64k segment. for example.... $30000 UPDATE_ADDR_HL MACRO move.w H,SCRATCH ; H into Scratch reg lsl.w #8,SCRATCH ; shift up into high byte or.b L,SCRATCH ; fetch L into low byte move.l SCRATCH,HL ; Update HL ENDM UPDATE_ADDR_BC MACRO move.w B,SCRATCH ; B into Scratch reg lsl.w #8,SCRATCH ; shift up into high byte or.b C,SCRATCH ; fetch C into low byte move.l SCRATCH,BC ; Update BC ENDM UPDATE_ADDR_DE MACRO move.w D,SCRATCH ; D into Scratch reg lsl.w #8,SCRATCH ; shift up into high byte or.b E,SCRATCH ; fetch E into low byte move.l SCRATCH,DE ; Update DE ENDM I just want to caveat the above with that it would be a fallback when no optimised translate instructions could be used. For example adding 1 to H would go.. Code: move.w #1,SCRATCH add.w SCRATCH,HL add.b SCRATCH,H As the translated code runs each frame I'd opt for a Copper or VBL interrupt to read the memory mapped IO ports described in the MAME driver, the ISR would effectively do all of the Amiga side screen updates. The status register could be tricky (would need to store that somewhere possibly in D7?). One massive improvement a 68020 would have over this is that data regs can be used as address registers, so effectively... it would fly. Thoughts...? Am i crazy? Last edited by mcgeezer; 10 September 2019 at 19:09.