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Old 26 January 2021, 10:39   #6
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 45
Posts: 24,627
CPU chipset access always takes 2 DMA cycles. AGA CPU cycle access timing has not changed from OCS/ECS. Unfortunately. Only big difference is that AGA (and A3000) chip ram is 32-bit wide and long aligned 32-bit read or write is as fast as 16-bit read/write.

Writes are slightly faster because after chipset (budgie) has latched the data, CPU is free to continue in next CPU cycle.
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