Quote:
Originally Posted by Stedy
Am I missing something but after re-building the TF530 design from the Github sources and doing a post layout timing analysis, I get errors, see attached.
Have you tweaked anything in the UCF files for the JED files you supply for different speed bins?
BTW, using faster -7 CPLDs should not matter, you can always go to a faster grade, never a slower one as the part number details the maximum speed, which this design should not hit.
|
In my case 7ns cpld's isn't working of fully populated board. Withiut FPU it kinda works, however, i can not run any programs/games