Quote:
Originally Posted by Gorf
We are talking about next-gen here - so targeting a 7MHz 68000 is not necessary. But the performance problems on low end processors show, that there is room for improvement.
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Exactly, something that runs fine on a low end machine will just fly on a fast one !
Quote:
Originally Posted by Gorf
Can you give me some examples of code that take two or more instructions on 68k, but are just one instruction on RISC?
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An example of this is arm's predicate+barrelshifter. But they're not as useful as they pretend when alone, and nearly never used together.
So rather than one-liner examples, that can be biased toward some particular architecture, a whole routine would be better (especially one that puts some pressure on the register file).
Why not a code contest ?
Everyone interested designs his own ISA (or chooses an existing one to defend) and then writes some routine (doing something useful).
We could then finally see who's powerful and who's not.