Quote:
Originally Posted by Photon
2. To support early A1000 Blitter chips, the documentation says to read twice before the CPU can rely on the value. Copper blits need only to perform one blit wait and nothing else. Blitter interrupts are triggered by BBUSY and so need no wait.
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Are you really sure this only applies to the CPU? What happens, if we've got a lores display with 5 or 6 planes or a hires display with 3 or 4 planes and additionally all sprite channels are used? It would not make sense, if the blitter on the A1000 would always catch the first memory cycle, because bitplane DMA has always priority over the copper and the blitter in that order. The copper also needs in these cases two $0001,$0000 waitblits to be sure that the blitter is finished.
@Toni: Could you confirm this behaviour for these cases on the A1000?