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Old 19 August 2012, 16:30   #54
TheDarkCoder
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Join Date: Dec 2007
Location: Dark Kingdom
Posts: 211
Quote:
Originally Posted by StingRay View Post
Yep, that's exactly what I was talking about. This problem only happens on 68040/60 machines and can be avoided by writing to INTREQ twice. Might also be that just another access to a custom register is enough after writing to INTREQ but I always used the "write to INTREQ twice" approach.

AFAIR, I did many tests working on P61 610.6, and it resulted that just an access to a custom register, or a CIA register, gives a delay long enough to allow the clearing in INTREQ to "propagate" to the SR of the CPU. Maybe an access in chip ram is enough, too. That sound reasonable, since the speed of those accesses is fixed by Agnus and does not depend on the CPU speed
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