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thebajaguy · 25 February 2021, 01:01

One of the outstanding issues we need some hardware logic pros on is the 68040/68060 reading the nibble bits of hardware expansion cards, particularly the Zorro II cards. Some cards don't mind the way the CPUs access their registers, some balk at the read/write. To my best understanding, the CPUs all the way up to 68030 will read 16-bits or will 'bus-size', but when you get to the 68040 and 68060, the boards get hit with a 32-bit read no matter what you do. I can take a GVP HC8 w/4MB and drop it in my Buster 11 '030 A3000 and it's happy. I drop it in my A4000T a second later, and the DPRC is read fine, but the 4MB RAM reports 'BAD'. Beside taming the cache/burst item I noted above (not an issue during autoconfig - data cache is off), I don't know what might be possible with Buster, other than the note that Z2 speeds on a Buster are 2/3 of actual Zorro II in a native 68000 system.

Buster has some problems with timing that he mostly fixed with the last -11, but with modern FPGA logic speeds well ahead of the silicon gates he had to work with ~27 years ago, he can likely get ahead of the race conditions and address other logic that was needed for better bus arbitration.

25 February 2021, 01:01	#16
thebajaguy Registered User Join Date: Mar 2017 Location: Rhode Island / United States Posts: 203	One of the outstanding issues we need some hardware logic pros on is the 68040/68060 reading the nibble bits of hardware expansion cards, particularly the Zorro II cards. Some cards don't mind the way the CPUs access their registers, some balk at the read/write. To my best understanding, the CPUs all the way up to 68030 will read 16-bits or will 'bus-size', but when you get to the 68040 and 68060, the boards get hit with a 32-bit read no matter what you do. I can take a GVP HC8 w/4MB and drop it in my Buster 11 '030 A3000 and it's happy. I drop it in my A4000T a second later, and the DPRC is read fine, but the 4MB RAM reports 'BAD'. Beside taming the cache/burst item I noted above (not an issue during autoconfig - data cache is off), I don't know what might be possible with Buster, other than the note that Z2 speeds on a Buster are 2/3 of actual Zorro II in a native 68000 system. Buster has some problems with timing that he mostly fixed with the last -11, but with modern FPGA logic speeds well ahead of the silicon gates he had to work with ~27 years ago, he can likely get ahead of the race conditions and address other logic that was needed for better bus arbitration.