Thread: Copper timing
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Old 20 July 2008, 17:12   #17
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 45
Posts: 23,794
Originally Posted by yaqube View Post
"/BLIT" is another name for "/DBR". In all functional descriptions in Technical Reference and Service Manuals for A500/A2000 the name "/DBR" is used but in schematics it's named "/BLIT". It prevents CPU from getting bus access in current cycle.

"/REGEN" is an output from CPU address decoder. It's only active when CPU wants to access custom registers.
Ah, that explains it

According to my tests:

As for 3: it apears that this cycle doesn't have to be a write to copins. It can also be a bitplane dma fetch.

As for 4: it apears that this cycle must be a free bus cycle. If it's taken by bitplane dma another cycle is required.
Ok, I'll test if other DMA channels can also use that cycle.
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