Thread: Cycle-exact
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Old 14 January 2019, 08:46   #7
MarkW
 
Posts: n/a
Just to wrap things up here - for future reference.

The reply of Galahad/FLT is out in the woods. I have done some pixel counting and it's very clear that A500 hires resolution is not 640x512, but 640x256. So there should be no interlacing.

Here are the images:


Cut out of the windowed area is 640x512, but the pixel height is two pixels - look at the trashcan. So it's effective 640x256.


As roondar mentioned, it's just a working hypothesis that the CPU loop is not aligned with DMA cycle boundaries - and that's good enough for me.

But, as with any hypothesis, it could be cool to test this on a real A500. I would do it myself, if I had the hardware...
 
 
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