Quote:
Originally Posted by Dimlow
I wish there was a way i could just suck up all this FPGA knowledge that that you guys have. My learning seems to be going so slow. All i have managed to do so far is flash a few leds on the dev board.
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In my case, I have learned VHDL at school 12 years ago, it was for ASIC design.
Then, in 2004-2005, with the C-One phenomena, my interest for VHDL came back. At the same time, the dev boards started becoming affordable. I was able to get two boards at work for some serious projects.
1943 is the first "fun" project I have made.
I recommend the website fpga4fun to start with FPGA.
The hard part with VHDL is the sequential logic with state machines and pipelines.
Some recommendation for the VHDL processes :
- Your first IF should be the asynchronous reset condition with the power-up init for the registers : IF (reset = '1') THEN
- Then, you have a : ELSIF rising_edge(clock) THEN
- Every assignment after the THEN is synchronous with the clock.
- Here, you can have additional IF conditions : they will be translated to clock enable, count enable, synchronous clear or set to registers or counters.
- You can also use CASE() .. WHEN => when you want to create a state machine.
Regards,
Frederic