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alexh · 29 January 2014, 13:42

For IDE we should be able to re-use the Gayle IDE re-implementation from the CFIDE68k project. However I believe that is written in ABEL which isn't a particularly flexible HDL.

Once converted to VHDL/Verilog you won't need to use the same CPLD. You could use a larger one with enough pins and slices to implement either SRAM or DRAM memory expansion.

29 January 2014, 13:42	#4
alexh Thalion Webshrine Join Date: Jan 2004 Location: Oxford Posts: 14,354	For IDE we should be able to re-use the Gayle IDE re-implementation from the CFIDE68k project. However I believe that is written in ABEL which isn't a particularly flexible HDL. Once converted to VHDL/Verilog you won't need to use the same CPLD. You could use a larger one with enough pins and slices to implement either SRAM or DRAM memory expansion.