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Old 18 August 2012, 17:23   #150
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Join Date: Dec 2010
Location: Wisconsin USA
Age: 55
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Originally Posted by Schoenfeld View Post
Here's a quick hack: Disabled one of the two 64M banks and added a simple equation that pulls STERM as soon as AS becomes valid on the area. CPU is a 68030RP25C, clocked at 25MHz. This looks like a single cycle to me:

However, you also see a problem with ECS and cache active: If the CPU hits a valid cache entry, the time until the next ECS is very short. Now if you open a row "just in case", you must go through the whole cycle of precharge and Precharge-to-row-open time before you can open the next row. Trouble is that the CPU may start the next access no more than two cycles after that, and you must be ready, otherwise you don't win but even lose time.

Disabling the cache makes sure that there's always an access after ECS:

At true 0-waitstate, I wanted to know the difference between "cache and no cache", so I tried bustest. First with all caches disabled:

...and then with all caches on (which also turns caches&burst on for the Bustest inner loop):

...and this looks like a measurement error to me, 'cause the read values are too close together. Write value is even more of an indication of a measurement error, because Cache is not updated on writes. Only the fastmem, which gains a lot from bursts, is a tiny bit faster.

I may be a memory cycle short to complete the time after precharge, but this quick measurement hack shows me that my idea of "external cache equals internal cache performance" is close to being correct. You must be right in terms of "burst helps", because fastmem with cache+burst is faster than the 0-waitstate area.

I'll need triple memory speed vs. CPU speed to really become fast enough to "play cache". Is it worth it? Not sure. I have to sacrifice at least one pin on the logic chip, and pins is what I'm always short of. I'd have to work on the memory controller in terms of "close the row ASAP if no access" in order to work with cache, and I need more state-bits for the memory controller because I need to stretch burst accesses. Need to draw some state diagrams...

You just confirmed a zero wait state synchronous cycle takes 2 clocks! Remember AS is negated 1/2 clock before the cycle ends. The best way to avoid the row open and pre-charge penalties is to qualify the start of your memory cycle with AS since an external cycle can be aborted after ECS is asserted. ECS is more practical for SRAM based cache (no penalty if cycle aborts) or DRAM refresh arbitration. Another potential problem with ECS is address valid times are not guaranteed with ECS assertion since the address bus often has a greater device or capacitive load and/or address buffers before memory logic (but the on board logic may delay RAS assertion long enough to solve that problem).

I have found Bustest to be most accurate with the instruction cache enabled and data cache disabled. Even so, Bustest results can vary for a number of reasons:

Also, please remember that Burst is a cache mode so if you disable the cache you also disable Burst!


Last edited by SpeedGeek; 18 August 2012 at 17:46.
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