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Old 21 May 2018, 12:04   #5
RedskullDC
Digital Corruption

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Join Date: Jan 2007
Location: Dorrigo/Australia
Age: 56
Posts: 337
Quote:
Originally Posted by Toni Wilen View Post
Every FPGA chip equipped DKB board ROM dump I have seen has few kilobytes of "random" looking data at the end of the ROM image.

Xilinx XC3000 series chips allow configuration from a Byte wide source, either from address $0000 up, or from $FFFF down:


Table 1: Configuration Mode Choices
M0 M1 M2 CCLK Mode Data
0 0 0 output Master Bit Serial
0 0 1 output Master Byte Wide Addr. = 0000 up
0 1 1 output Master Byte Wide Addr. = FFFF down
1 0 1 output Peripheral Byte Wide
1 1 1 input Slave Bit Serial


From Toni's observation, sounds like it is configured as $FFFF down mode, and initialises the FPGA from the code at the end of the ROM image.

Good luck with it

Cheers,
Red
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