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BlankVector · 01 May 2019, 17:46

I'm currently improving Slow RAM detection in EmuTOS with WinUAE 4.2.0 64-bit, and I suspect a WinUAE bug with JIT and cache.
Basically, presence of RAM is detected by writing a single LONG at the start of an address block, and reading it back.

I used the documentation below as reference:
https://www.amigacoding.com/index.php/Amiga_memory_map

Here is what I understood. Please correct me if I'm wrong.

- If present, Slow RAM starts at $00C00000.
- It normally ends at $00D80000, for a maximum of 1.5 MB.
- Some extension boards have a "Gary adapter" which adds additional 256 KB at the end, for a total of 1.75 MB (called "1.8 MB" by WinUAE). In such case, the Slow RAM ends at $00DC0000. As this overrides the Gayle IDE address space, this kind of extension is incompatible with the Gayle chip present in A600/A1200.

So if Gayle is not detected (A600 IDE and PCMCIA disabled in WinUAE), I try to detect Slow RAM up to $00DC0000 (exclusive). Typical setup is A4000 (no Gayle) + 1.5 MB of Slow RAM.

My problem occurs at address $00D80000 (just after the end of official 1.5 MB Slow RAM).
- With 68030 + instruction cache enabled by software + data cache disabled by software + more compatible + no-JIT: OK, no RAM is detected at $00D80000, as expected.
- With same setup but with JIT enabled, some RAM is detected at the very same address. I don't know how much, as I only test the first long word.
- With same setup, JIT enabled but instruction cache disabled by software, it works again.

So it seems there is a bug in WinUAE with the following configuration:
- 68030
- instruction cache enabled by software (CACR = $00000001)
- JIT

As there is no cache management in my RAM detection routine, the issue could come from the presence of data cache. But as data cache is disabled both in WinUAE settings and CACR, this should not happen. And there should be no difference between JIT and non-JIT.

I suspect some kind of incorrect correlation between instruction cache and data cache when JIT is enabled. Strangely this does not happen if I setup only 1MB of Slow RAM (ends at $00D00000).
Other possibility would be incorrect handling of $00D80000 address when JIT is enabled.

Any hint will be welcome.

Of course, I can provide a testcase if necessary.

01 May 2019, 17:46	#1
BlankVector Registered User Join Date: Jun 2012 Location: France Posts: 183	Slow RAM detection & JIT I'm currently improving Slow RAM detection in EmuTOS with WinUAE 4.2.0 64-bit, and I suspect a WinUAE bug with JIT and cache. Basically, presence of RAM is detected by writing a single LONG at the start of an address block, and reading it back. I used the documentation below as reference: https://www.amigacoding.com/index.php/Amiga_memory_map Here is what I understood. Please correct me if I'm wrong. - If present, Slow RAM starts at $00C00000. - It normally ends at $00D80000, for a maximum of 1.5 MB. - Some extension boards have a "Gary adapter" which adds additional 256 KB at the end, for a total of 1.75 MB (called "1.8 MB" by WinUAE). In such case, the Slow RAM ends at $00DC0000. As this overrides the Gayle IDE address space, this kind of extension is incompatible with the Gayle chip present in A600/A1200. So if Gayle is not detected (A600 IDE and PCMCIA disabled in WinUAE), I try to detect Slow RAM up to $00DC0000 (exclusive). Typical setup is A4000 (no Gayle) + 1.5 MB of Slow RAM. My problem occurs at address $00D80000 (just after the end of official 1.5 MB Slow RAM). - With 68030 + instruction cache enabled by software + data cache disabled by software + more compatible + no-JIT: OK, no RAM is detected at $00D80000, as expected. - With same setup but with JIT enabled, some RAM is detected at the very same address. I don't know how much, as I only test the first long word. - With same setup, JIT enabled but instruction cache disabled by software, it works again. So it seems there is a bug in WinUAE with the following configuration: - 68030 - instruction cache enabled by software (CACR = $00000001) - JIT As there is no cache management in my RAM detection routine, the issue could come from the presence of data cache. But as data cache is disabled both in WinUAE settings and CACR, this should not happen. And there should be no difference between JIT and non-JIT. I suspect some kind of incorrect correlation between instruction cache and data cache when JIT is enabled. Strangely this does not happen if I setup only 1MB of Slow RAM (ends at $00D00000). Other possibility would be incorrect handling of $00D80000 address when JIT is enabled. Any hint will be welcome. Of course, I can provide a testcase if necessary.