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Old 26 August 2018, 13:26   #215
roondar
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Join Date: Jul 2015
Location: The Netherlands
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Quote:
Originally Posted by Megol View Post
Up to at least 1984 there were no fast page mode, only page mode. Fast memories had a minimum cycle time of about 230ns with full RAS/CAS, down to about 120ns in page mode (there were however at least one chip with an 100ns page mode timing in 1984).
Most of the DRAM was much slower.
I think I finally get it. With the small disclaimer I am not a RAM chip expert.

See, something had been bothering me about the BBC Micro vs Amiga example - the RAM used in the BBC Micro was 100ns, but the system only accessed it at 250ns (4MHz clock, 1 access per cycle = 250ns - or if you prefer, 2MHz clock, 2 accesses per cycle = 250ns). That didn't make any sense to me, why access memory at only 40% of it's access speed? Same with the Amiga's 280ns maximum access speed on 150ns RAM (only 53% of access speed).

But now I think I do. What's happening is that these systems don't use page mode. They use random-access mode. And memory used for random access is much slower than it's rated (page mode) speed.

Just check the datasheets: the KM4164B-10 used in the BBC Micro has a random access cycle of 190ns. That's a lot closer to the actual memory access speed of the system than 100ns is. Similarly, for the 41256-15 commonly used in the early Amigas the random access cycle is 260ns. That is really close to the 280ns the system accesses memory at.

Given this data, it makes a great deal of sense these systems where the way they are: these where CPU's without a cache. Both the CPU & DMA can (and do) request any memory address at any time in systems like this. It'd be a nightmare to try and make a memory controller that deals with that and still tries to keep the RAM running in page mode most of the time.

Last edited by roondar; 26 August 2018 at 13:44.
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