Thread: 68k details
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Old 26 August 2018, 10:03   #212
plasmab's Avatar
Join Date: Sep 2016
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Originally Posted by Bruce Abbott View Post
Yes, RAM was generally the most expensive part. Commodore originally wanted the A1000 to have only 128k on the motherboard, to keep costs down.

But support chips also have propagation delays which need to be minimized. In 1983 the cheap high speed low power options we have today were not available, so faster chips were more expensive and drew a lot more power - requiring a more expensive power supply, better heat-sinking or fan cooling etc., all of which could raise the cost significantly.

And as timing approaches the minimum the design gets more critical, less tolerant of things like PCB layout and component variations, and generally harder to get right. Development costs go up, reliability goes down. Running at the ragged edge to get a little better performance might sound like a good idea, but would be a disaster if 1 in 100 machines randomly crashed or had visible glitches.
Agree in general but the 74LS series was available and used in the BBC B. I guess the ASIC tech may have been more basic. Thinking about it.. the most difficult thing for a memory controller to do a the time would be address decoding to make sure that the address in question was actually for RAM.

PCB routing isnt much of an issues in terms of delays. A signal can travel 1 meter in 3.3ns in copper and around 5-7ns/m in "clean" semiconductors (this is an intentional simplification and I know ALL the details about calculating this for variously doped semiconductors of all varieties). The gate to gate delays is the biggest factor i can think of.

So I would have designed the 68000 bus interface to place the address on the bus in S0, assert AS on the falling edge of the clock and then latch the data (for a read) on the next postive edge of the clock unless an "I'm not ready" signal is asserted.

Why would i have done this?.... because if i was sitting in a room designing a chip in 1978 I would have been able to see that component speeds were improving all the time and I would have been thinking about how my design could take advantage of that.

But I wasnt in the room. None of us can say what the outcomes of the meetings they had on it were. What tools they could have used if they'd been willing to pay. What quotes they had for things. For all I know the chief designer wanted to do it my way and was shot down by his boss/manager. That has happened to me more than once in my career. So I am not blaming anyone or saying the chip is crap. I am just dreaming about what might have been.
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