Quote:
Originally Posted by roondar
The numbers you mention seem wrong, a move from d(an,ix) is never as low as 10 cycles. For reference, I use this site for my CPU timing info: http://oldwww.nvg.ntnu.no/amiga/MC68...000timing.HTML
Anyway, the numbers in parentheses show the number of memory read/write cycles/actions the instruction causes on the bus, the number in front of the parentheses shows the number of cycles the instruction takes.
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Then simply compare this to the speed of the CPU, which does about 7 million cycles per second/140.000 cycles per PAL frame. |
Thank you, that site looks to have all the data and even explains it, and says, as hooverphonique did, "The size of the index register (ix) does not affect execution time".