View Single Post
Old 09 December 2019, 01:24   #30
Registered User

solarmon's Avatar
Join Date: Dec 2018
Location: UK
Posts: 677
I'm so glad you found the issue! Great job!

That is a really interesting issue! A great one for the knowledge base.

This is why I drew up my diagram - to try to show what components could impact the reset signals. I'm glad it may of been some use to someone.

It is interesting how the IPL lines lines were impacted by this issue and how this manifest itself in Diagrom.

It is clear now that the _RST signal was not being pulled up to VCC properly - it was effectively floating (if so, a logic prove should show this - it would not be high or low), unless the other _RST pins was keeping it from being floating.

Well done again, and for persevering with it!
solarmon is offline  
Page generated in 0.04606 seconds with 11 queries