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Originally Posted by Pyromania
how does it compare to OSSC?
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Well that kind of depends where the project goes. At its simplest it's basically doing exactly the same as an OSSC but internally.
In *theory* however if you replace Denise with an suitable sized FPGA you could then do all sorts of clever stuff that the OSSC wouldn't even come close to. The OSSC can only rework what is already there, a Denise replacement could potentially include having some AGA functionality (or better) on an A500/A2000.
I'm not even going to pretend to understand how to write Verilog (I looked at it, I understand about 5% at most
) but the MiSTer has the code for the hardware emulation of Lisa/AGA so again this isn't someone needs to start from scratch programming a Lisa replacement.
I don't believe you could do any RTG (feel free anyone who actually knows what they're talking about to tell me I'm talking crap at any point) without a new processor however because the drivers need an '020 or better but you might be able to do some other stuff.
If anyone is clever enough to write Verilog then you could experiment now. As far as I can see it's a single wire definition in the MiSTer code base each to enable ECS or AGA in "Denise" so a bit of config and you could have MiSTer running a virtual A500 with the rest of the ECS chipset, a 68k and AGA Denise!