I think where Pandy71 is getting caught up is -
If the Host (7 mhz CPU) is held in RESET then the ECLK can not be generated by that CPU. As such will fail when handling VMA/VPA and E
Personally I am unsure if after BG/BA handshaking the HOST CPU in to RST and letting the other (14Mhz) carry on - will the HOST CPU would still burst ECLK while RST?.
Another concern is what about the Target CPU running at 14Mhz, what about the 7Mhz Bus, we will need to slow-down to negotiate that (DTACK)... the cache will help immensely here
Hmmmm.... looks like I may need to dust off the 'ol 68000 bible again =)
A very smart chap - Livio Plos actually produced a working 14Mhz version (without cache) and based on simple 74 logic.... it should also be simple to augment the design with 16KB of Cache.
@SpeedGeek
If you are interested I have an A500 Rev 1.3 motherboard here for fun and games if you want it.
@Pandy
A two layer board
reasonably designed should see 28 / 33Mhz frequency operation.