Originally Posted by Mr B
5% higher performance without FPU, or, 5% lower, with a FPU that, at best, has a spotty support anyway... I can see why he went with this route. It's also cheaper to produce, which may be a factor. And, he did include the socket space, so if anyone wants to, it's still an option.
If acatune had an FPU profile that would be pretty cool - I personally would like to run Ray tracing and 3D modeling on my 1200 (yes sometimes I'm a masochist).
Edit: just saw Jens reply:
Originally Posted by Schoenfeld
That compatibility mode would mean extra states in the memory controller state machine, which is next to impossible with the amount of logic already fitted in these small 9572 CPLDs.
The problematic thing with FPU as additional load on the data bus is burst. If you switch off burst, it's likely that the board is stable. However, since I can't test it with the specific FPU that you have chosen (there's a bunch of different masks), I can't guarantee it.
I need satisfied customers, because I need you guys to recommend my products to each other. If I promised anything that I can't keep, you'd complain (and you'd be right about it!). I've tried to make the ACA1233-40 as "hackable" as possible, for example by keeping the holes for the PGA FPU open and adding a space for a canned oscillator, so you have a choice of sync clocking (just close the solder-jumper) or async with the canned oscillator (that's an either-or choice, you should not close the jumper and install a canned oscillator at the same time).
Who knows, maybe such a hacked unit is even stable with your choice of FPU? The select/autodetect logic is all there. Just don't hold me responsible if it doesn't work. It's a hack, and you are responsible for it.
Ok that is much more involved than I suspected, thanks for the detailed reply, it is appreciated.
What are the chances of you doing an FPGA accelerator now that Apollo core etc seems to be at a useful state? (Iirc it's effectively a very very fast 060?)