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Old 16 November 2014, 19:22   #192
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 44
Posts: 23,586
Originally Posted by mc6809e View Post
According to the Agnus specifications document on the EAB file server, VBlank actually begins at the beginning of the last line (not that documentation can always be trusted).
Document shows Agnus output sync signals, vblank signal is not same as vblank strobe (that Paula sees and generates vblank interrupt). Vblank starts at the beginning of line 0. (or 1 if A1000 Agnus). Very easy to see in logic analyzer (and tested many times long time ago)

I don't see anything undocumented in this case
DMA/CPU timing shouldn't have any undocumented features left. (Not including >=68020 CPU internal timing)
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